Expected final report¶
The final report (maximum 6 pages) should contain:
Theorical demonstration of the behavior of the TSPC dff cell. This demonstration should explain the state of transistors (on / off) and internal nodes (0, 1, 0z, 1z) of the cell before and after all the possible transition (rising of falling) of one of the inputs (CLK or D).
A figure of the designed layout:
Explain the way you tried to floorplan the layout.
Criticize your own work taking into account the following facts:
Long lines of polysilicon are weak connections.
To many contacts (M1/Poly, or M1/Active) add parasitic resistance to lines.
Metal2 should be avoided in order to ease automatic routing phases.
The final plots of the “Propagation time of the INVX1 cell” and “Propagation time of the TSPCFF cell”.
Compare the mean magnitude of the two set of results, and try to explain the difference.
For the first set of results (INVX1) we see that the effect of the input slope can not easily be isolated from the effect of the load capacitance. Is it true for the TSPCFF cell ? Why ?
The several plots obtained for the Tsetup measurements. We didn’t ask anything about the “Hold Time” of the DFF. Explain what kind of testbench can be used to extract this information. Do you think that we can use the same kind of optimization as for the Tsetup time ? (Explain).
Put the sources of “testbench.sv” and “board.vams” of the final simulation in your report.