Setup time

We now try to extract the setup time of the TSPCFF flipflop. The setup time of a flip flop can not be directly measured, you have to stick to the definition of the setup time in order to find a way to access to this value.

From a purely digital world point of view:

  • the setup-time is the least allowed time for a transition of D before a rising edge of the clock

From an electrical point of view:

  • the DFF may goes to a metastable state when the delay between the D input transition to the CLK input transition is to small.

  • From a practical point of view , the propagation time of the DFF will increase when this delay is to small.

Our first objective is to check this behavior of the DFF for short setup time.

Setup time behavior exploration

  1. Create a new template_dir based on the previous TSPCFF simulation

  2. Rename this template_dir TSPCFF_setup_explore

  3. Get into this directory, and modify the testbench according the following explanations:

  4. Change the data input slope (din_tt_val) to ** 0.10ns**

  5. Modify the loops in order to check results only for one capacitor value (11fF) and one clock slope value (0.10 ns). In order to do that, just change the index bounds of the loops on slope_index and capa_index

  6. Modify the input sequence in order to have din and clk input rising at the same time !:

  • setup clk and d to 0

  • wait for stable signals (#(digital_tick))

  • setup clk to 1, in order to store a 0 in the d fliflop

  • wait for stable signals…

  • setup clk to 0,

  • wait for stable signals

  • setup d to 1 and clk to 1 at the same time !!!

  • wait for stable signals and get the measured propagation time and store the result

  1. Add now a third loop around the sequence, in order to change the delay between de D input and clock input. For that purpose we will use the clk_delay_val variable. You should get something like:

initial...
int slope_index, capa_index, clk_delay_val_index ;

... main loop

...secondary loop (reduced to only one index)

-- third loop (reduced to only one index)

for(clk_delay_val_index=10; clk_delay_val_index >=0; clk_delay_val_index--) begin
    ...
   clk_delay_val = delay_val_index*10.0e-12 ;
   ...
end

...

With this new loop you will test the DFF with smaller and smaller setup time…

  1. Modify the output results (fwrite(...)) in order to write the value of the propagation time for each value of the chosen setup time. Examine the results

  2. You may modify the plot.py script in order to plot the evolution of the propagation time as a function of the chosen setup time.

You should see  an increasing propagation time. So now, you should reconsider propagation time evaluation related to setup time !!!.

Combined extraction of setup and propagation time

When used in a  synchronous design, the maximum operating frequency is limited by the critical path of the combinational parts and the characteristics of the D flipflops according to the following equation:

Tmax > Tprop + Tcomb + Tsetup

Where:

  • Tmax is the period of the clock

  • Tprop is the propagation time of the driving DFF

  • Tcomb is the propagation time of the combinational part between the two DFF

  • Tsetup is the setup time of the receiving DFF

According to this equation we can try to minimize  Tmax, using the minimum value of Tprop+Tsetup, with the hypothesis that the two DFFs are identical.

  1. Generate a plot of  Tprop+Tsetup as a function of the choosen Tsetup. Choose appropriate bounds in order to show explicitly the minimum of the curve.

We now want to have an automatic extraction of the minimum.

  1. Modify the test-bench in order to find the minimum using a dichotomy algorithm. Do not forget to define a stop criteria to the dichotomy (for example an accuracy of 0.5ps)

You should now be able to reconsider the propagation time evaluation of previous chapter. As propagation time is linked to setup time, you should be able to setup a combined extraction of the propagation time and the setup time, taking into account the load capacitance…

Bonus: What about hold-time ?

  1. Imagine a way to extract the hold-time of the flip-flop.

  2. Check if the hold-time is linked to setup-time

  3. Imagine a way to make a combined extraction of (hold-time, setup-time and propagation-time)