Rise propagation time of the TSPCFF

Usefull parameters for a D flip-flop

 For a D flipflop, useful values are, for example:

  • The propagation time from the CLK input to the Q output.

  • The setup time of the D input referenced to the CLK arrival time.

  • The hold time of the D input referenced to the CLK arrival time.

More precisely:

For a given choice of (technological case, power supply, temperature), the informations needed by the front-end tools for timing analysis including D flipflops are:

  1. Propagation time from the input  CLK to the output Q as a function of :

    • The rise time of the input clock  CLK

    • The capacitive load connected to the output

  2. Setup Time of input  D relative to input CLK as a function of :

    • The rise time of the input clock CLK

    • The fall/rise time of the input D

  3. Hold Time of input  D relative to input CLK as a  function of :

    • The rise time of the input clock CLK

    • The fall/rise time of the input D

We now, try to extract the propagation time of the TSPCFF fliflop. We will limit us to a rise time of the output Q. Remember that the propagation time of a D flipflop is from the rising CLK to a changing output.

Code update: board.vams

The board.vams code needs strong modifications.

First of all, we need two signals to drive the flip-flop : a clock signal, and  input data signal.

  1. Add a new digital signal “clk_logic” in the port list of the board (dont forget to add a specific line in the “IO defs” part, and in the “// Nature of signal” part.

  2. Change the name of the “tt_val”  variable to “din_tt_val” everywhere in the file (each input signal will have a specific transition time)

  3. Add a new variable “clk_tt_val” of the same kind of “din_tt_val”

  4. Add a new internal signal named “clk_electrical”  (in the //Internal signals) part of the code

  5. In the part “//Here we generate…, change the transition time of the cmos_transition_generator to “.tt_val(din_tt_val)”…

  6. Add a new cmos_transition generator for the clock (in the part “//Here we generate…). Input should be “clk_logic”, output should be “clk_electrical”, tt_val should be “clk_tt_val”.

  7. Replace the INVX1 device under test by your flipflop:

    • The d input should be connected to din_electrical

    • The clk input should be connected to clk_electrical

    • The q output should be connected to dout_electrical

  8. Modify the edge detection in order to measure the propagation time from a clk transition to an output transition.

Code update: testbench.sv

The testbench.sv code need strong modifications.

  1. Add a new “logic” clock signal named clk in the “// logical signals” part of the code

  2. Change the name of the tt_val signal to din_tt_val

  3. Change the name of the delay_val signal to din_delay_val

  4. Create to new real signals “clk_tt_val” and “clk_delay_val”

For propagation time measurement, from clock to output data, we do not take into account the transition time of the data input.We will choose a fixed value of 10ps. Furthermore, we will not add any supplementary delay to signals.

  1. At the beginning of the initial process, add the following lines:

din_tt_val = 10.0e-12 ;
din_delay_val = 0.0 ;
clk_delay_val = 0.0 ;

We have now to modify the main loop (// secondary loop) of the test-bench in order to generate a sequence of D flip-flop sampling  0, followed by sampling of 1 followed by a measurement. The sequence should be like this:

  • setup clk and d to 0

  • wait for stable signals (#(digital_tick)

  • setup clk to 1, in order to store a 0 in the d fliflop

  • wait for stable signals…

  • setup clk to 0,

  • wait for stable signals

  • setup d to 1

  • wait for stable signals

  • setup clk to 1

  • wait for stable signals get the measured propagation time and store it to the result file.

  1. Change the test-bench according to such a sequence

  2. Change all constant strings in testbench.sv and plot.py in order to generate the good comments…

  3. The original code, contains sequence to test if the behavior of the cet is really an invertor. We must modify also the sequence in order to check if the TSPCFF as the behavior of a D flip-flop.

Add the following code just before the initial process:

logic dout_ref ;
always @(posedge clk)
    dout_ref <= din ;

And then modify the comparison code:

// Then check if we have an expected value
if(dout != dout_ref) begin
    $fdisplay(STDERR,"\0....

Simulation

  1. Simulate, correct you errors, and show your work to the advisors…