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This course provides an overview of software and hardware design for smart objects. It is mandatory in the Smart Objects track. Software and hardware aspects, system integration, design and validation tools are studied. The main goal is to reach a sufficient level of understanding to design alone a prototype system embedding one or several digital hardware operators for the processing and a micro-processor, plus its peripherals, for the control. A hands-on approach is taken, with the aid of state-of-the-art laboratory equipment. During the final project the students design an actual prototype on a FPGA-based prototyping board, design the embedded software, connect the board to a host PC and test their application.

The labs are not graded. The lab reports and their source code files are not evaluated. The automatic evaluation system is informative only, the results it provides are not considered for the grading.

The final project accounts for 50% of the overall mark. You will work in teams of three. The same grade will be given to all members of a team. The grading is based on the project report and source codes. Reports must be written in Markdown format in a REPORT.md file stored at the root of the project's dedicated directory. The report and all source codes must be pushed in at least one of the personal branches of the team members (see below the section about labs for more information about the git repository and the personal branches) the day before the written exam at 23:59. After this deadline the git repository will become read-only and there will be no way to submit anything new. Clearly indicate in the project report which of the personal branches contains the report and the source code files. Do not forget to also indicate the names and email addresses of the members of the team. Example of report header:

# Project report: THE TIME MACHINE

The report and all source files can be found in the `doc.who` branch.

## Team members:

* H. G. Wells, h.g.wells@time-travel.org
* Doctor Who, doc.who@bbc.uk
* Poul Anderson, p.anderson@time.patrol.us
				

A two hours written exam, with documents, accounts for the other 50% of the overall mark. Connected devices (laptops, smartphones, tablets...) are not allowed. Example past exams:

The rules for retake exams are different and depend on the specific circumstances (number of students, remote or not...)

The labs are not graded. The lab reports and their source code files are not evaluated. The automatic evaluation system is informative only, the results it provides are not considered for the grading.

The labs are mandatory in the sense that you must work on each lab. If you do not you will very likely miss something important.

Attending the lab or the project sessions is warmly advised but not mandatory. If you cannot attend a lab session do your very best to complete the lab anyway before the following session. If you do not you will fall behind and it will become more and more difficult to catch up.

Writing a report for each lab and committing-pushing it with the source code files is warmly adviced but not mandatory. These files are for your own records only.

The lab sessions and the final project are entirely remote and use Zoom. If you prefer working at EURECOM the class room is 152. Do not forget to bring your own laptop, a headset and the Zybo kit. All labs and the final project are distributed and managed using git and GitLab.

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Books available in EURECOM's library

Online books

Standard VHDL packages

Miscellaneous