As the performance of a processor based system depends largely on the available memory bandwidth, the performance of a gate array (FPGA) is intertwined with its interconnect speed and density. 70% of the FPGA area is thus interconnect switches and buffers. This is not a surprise, because memory and interconnect are nothing but two sides of the same coin. While one bit of memory transfers one bit of information from point A in time to point B in time, a 1 bit wire transfers 1 bit of information from point A to point B in space.

Flash memory chips already use multivalued (MLC) flash transistors to increase density. In this research we try increasing interconnect density by using multi-valued routing wires, i.e 4 voltage levels to encode 2 bits of information. Things get much more technical from here as handling 4-valued signals with binary switches is not evident. Check out this article to see how we try to implement this with FDSOI transistors (not possible with ordinary CMOS).