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Maria Mushtaq

Safe and Secure Hardware (SSH) Team

COMELEC Department Telecom-Paris

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About me

Dr Maria Mushtaq is an Associate Professor in the Safe and Secure Hardware (SSH) Team at COMELEC Department, Telecom Paris, France. She earned her PhD from Université Bretagne Sud, France, focusing on "Software-based Detection and Mitigation of Microarchitectural Attacks on Intel's x86 Architecture", followed by a prestigious CNRS Excellence PostDoc position at LIRMM, Université de Montpellier. Her research interests lie in Microarchitectural security, Side-channel attacks & mitigations and AI-driven vulnerability assessment mechanisms for embedded systems.

Currently, she is focused on side channel analysis, discovery of known and un-known vulnerabilities, exploration of simulators for trace analysis on modern architectures i.e., Intel, ARM, RISC-V. She is supervising multiple Postdoc, PhDs and Master Interns on the topic. Maria is involved in multiple program committees including 2 top tier security conferences (ASIACCS & CHES). She is also the organizer of MICSEC Winter School with a deep focus on microarchitectural security.

Research Areas

We organize our work across the following themes.

Microarchitectural Attacks & Defenses

Developing and validating secure software modules, such as OS-level security primitives that protect against hardware vulnerabilities

Cryptanalysis & Software Security Components

Cache/branch leaks, transient execution, timing channels, and robust countermeasures.

  • x86
  • RISC-V
  • ARM
#Microarchitectural Attacks #Side-Channel Attacks
Virtual Platforms for Security Assesments

Virtual Platforms for Security Assessments Virtual prototyping to test security vulnerabilities without physical hardware.

  • Emulate processors and SoCs for safe, repeatable security testing.
  • Analyze microarchitectural flaws like speculation and cache side-channels.
  • Test OS-level defenses and runtime mitigation strategies in virtual setups.
#Hardware-Software Co-Simulation #SoC Emulation
AI based Hardware Security

AI-based Hardware Security – Leveraging artificial intelligence techniques to detect, predict, and mitigate hardware vulnerabilities.

  • Use machine learning models to identify anomalies, side-channel leaks
  • Apply AI for proactive threat detection—anticipating faults, attacks.
  • Enable adaptive defense strategies that continuously learn and evolve to counter emerging microarchitectural or hardware-level attacks.
#AI for Hardware Security #Machine Learning in Security

People

Research: Hardware security, microarchitectural leakage, formal verification, and secure SoC design.

Group Leader
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Dr. Maria Mushtaq

Associate Professor, COMELEC

Research: Hardware Security, Embedded Systems, ML, Side Channels Attacks at Telecom Paris.

Current PhD Students
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Muhammad AWAIS
PhD Student
Working on gem5 assisted hardaware accelorators for Side-channel attack detection.
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Nathanael SIMON
PhD Student
Working on Machine Learning Based Side-channel attack detection, Mainly focusing Reinforcement Learning.
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Mahreen Khan
PhD Student
Working of Hardware Performance Countermeasures for Side channels Attacks analysis
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Muhammad HASSAN
Working of Attacks Analysis and their mitigations using Simulation tools, mainly gem5
Former PhD Supervisons
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Loïc FRANCE
PhD Université de Montpellier
Study and evaluation of the impact of emerging technologies on memory vulnerabilities in embedded systems , PhD in Embedded Security, 2019-2022.
Montpellier
Currently Doing Post Doc from LIRMM.
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Natasha Alkhatib
PhD student C2S Chaire
Intrusion detection using Machine Learning for connected cars, PhD in Cybersecurity, 2019-2022.
Telecom Paris
Cybersecurity researcher and engineer at ETAS BOSCH.
Internship Supervisons
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Kolic Bogdana
Bachelors Project-IP Paris
Detection of Rowhammer Attack using HPCs and Machine Learning.
Telecom Paris
Currently Doing Masters from EPFL ETH.
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Samy Rida
Masters Project
Implementation of countermeasure techniques for cache-based timing side-channel attacks in multi- & many-core systems (3 Months).
Université Bretagne Sud, Lorient, France
Consultant in Cybersecurity SERMA SAFETY + Security
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Jeremy Bricq
Masters Project
Implementation of cache-based timing side-Channel attacks in multi- & many-core systems (3 Months).
Université Libre de Bruxelles, Belgium
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Matheus Victor
Bachelor in Eletrical Engineering, UFCG
Internship at Telecom Paris "Design and evaluation of RISC-V FPGA-based Testbed for Microarchitectural Side-Channel Vulnerabilities".
Telecom-Paris, France
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Maria Priscilla Lima Medeiros
Bachelor in Electrical Engineering UFCG
Currently doing a Postgraduate Diploma in Microelectronics at UFSM and an internship at Telecom Paris.
Telecom Paris, France
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Muhammad Emir
Masters in Embedded Systems
RTL based testing of side channel attacks on RISC-V processors.
Telecom Paris, France
Tenure (1st October-31st January)
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Gaetan Bois Baumann
Master CRYPTIS in Cryptology, Cybersecurity and Embedded Systems
Microarchitectural Side-Channel Attacks on ARM Architecture.
Telecom Paris, France, Future Ph.D Student at PQC shield
Tenure (2nd March-28th August)
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Hamza AARAB
Software for Embedded Systems, (UBO - Brest, France)
Micro-architectural side channel and covert channel attacks analysis on RISC-V Hardware.
Telecom Paris, France
Tenure (15th May-30th September)

Talks

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Latest Publications

Selected recent papers. For a full list, see Google Scholar.

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Contact

Reach out for collaborations, positions, or media.

Maria MUSHTAQ
Associate Professor
3B, Place Marguerite Perey
COMELEC, Telecom Paris
Cs 20031
Palaiseau, France

Email

@Maria_Mushtaq_

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