Design and optimization of a digital standard-cell

DocumentationΒΆ

  • GPDK045 Reference Manual

  • Design Rules

  • Spectre
    • Elements of syntax
    • Component instance
    • Some common primitives
    • Analysis commands
  • Verilog-A
    • Introduction
    • Module, Ports, Hierarchy
    • Data Types
    • Verilog-A Statements
    • Analog Operators
    • Event Driven Modeling


Table Of Contents

Part I: Virtuoso Environment

  • Design environment

Part II: INV cell Characterization

  • Introduction
  • Tutorial : Fall transition time of an invertor
  • Propagation times

Part III: TSPCFF design netlist preparation

  • TSPCFF netlist and environment preparation
  • Directory setup
  • TSPCFF netlist
  • Invertor parametrization

Part IV: TSPCFF cell Characterization

  • Rise propagation time of the TSPCFF
  • Setup time

Part V: TSPCFF cell Layout

  • Layout

Part VI: TSPCFF cell Final characterization

  • Introduction

Part VII: TSPCFF cell Optimization

  • Optimization strategy

Appendices

  • Documentation
    • Spectre
    • Verilog-A
  • Expected final report
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