Optimization strategy

_images/tspc-ff-schematic.png

Our goal is to minimize the overall “Tsetup+Tprop” time of the gate using transistor resizing, while keeping the following conditions:

  • The input capacitance of the clock input should not change.

  • The input capacitance of the D input should not change.

  • The fanout of the cell should not change

Given this conditions we should not change:

  • The transistors of INV_CK and INV_Q invertors

  • The MP1 ans MN1 transistors

We may try to modify the setup time using a resizing of all transistors connected to the \(\overline{\text{Ck}}\) signal:

  • MN4, MP2, MN2, MP5

TO BE COMPLETED