Overview"Those who fail to plan, plan to fail...". Architects, tailors, and directors all use plans (or models) for their creation, and software engineers are no exception. Thus, it is a common practice for software project managers to rely on the UML langage to document their software projects, and to perform modeling of the software itself.
The course tackles the use of UML (Unified Modeling Language) and SysML (System Modeling Language) in the context of embedded systems, specifically smart objects, in preparation for software design in industry. This course addresses all development stages of an embedded system, i.e. requirement capture, analysis, design, validation, and automated code generation. Validation includes the simulation of a model and the formal/mathematical verification of properties, e.g., proving that reaching a given error state is not possible.
The course is practice-oriented, including a modeling-based final exam in the lab room (Eurecom). "Real-world" case studies, such as those taken from avionic or automotive systems, are used in lab sessions.
This course was elaborated with Pierre de Saqui-Sannes, ISAE Sup'Aero.
- Overview of UML/SysML
- System requirements, analysis and design with SysML
- Model validation: simulation, formal verification, code generation and execution
- Modeling real systems (e.g. automotive systems)