Laurent Pautet

Computer and Network Sciences Department
Télécom ParisTech

Address     46, rue Barrault - 75013 Paris, France
Phone     (+33|0) 1-45-81-73-22
Fax     (+33|0) 1-45-81-31-19
Email     Laurent.Pautet@telecom-paristech.fr



Position

Short Biography

Research Topics

Research Activities

Real-Time Systems

I have been studying and designing real-time task scheduling algorithms, and their implementation in the operating system (OS), that address the challenges associated with multi-core platforms. For instance, a recent contribution on scheduling for mixed-criticality systems, which was developed in collaboration with Renault in the context of the IRT SystemX (thesis Gratia, project ELA), was shown to outperform previous approaches in terms of processor utilisation as well as the number of task preemptions. Another strong contribution on scheduling mixed-critical dependant real-time tasks was proposed in the context of the ISC chair was also shown to outperform the state of the art (thesis Medina).

Deterministic Platforms

Complementing the work on task scheduling, I am additionally exploring the use of deterministic and time-predictable computing platforms. The goal of this work is to improve the analysability of critical software in terms of its worst-case behaviour, while ensuring competitive performance in the average case. Predictability can be ensured in software using hypervisors on off-the-shelf hardware, as demonstrated in a collaboration with Thales Avionics (thesis Jean). The hypervisor intercepts accesses to shared resources (e.g., memory) and thus can manage these accesses to avoid contention and improve isolation. The quality of this work has been acknowledged through a best Paper Award and resulted in a joint patent with Thales.

Another means to improve the predictability of a platform is through specialised hardware. Current work (thesis Hebbache) aims at improving the average-case performance of the memory hierarchy of the Patmos multi-core platform by using dynamic arbitration schemes that converge to predictable Time-Division Multiplexing (TDM) in the worst-case.

Critical Systems Design Process

The research cited above aims at providing a suitable computing platform (OS, runtime, hardware) for critical real-time systems. A third pillar of my research activities are techniques and tools that help to design such systems via model-based design — exploiting, among others, the aforementioned computing platforms. Etienne Borde and myself strongly contribute to the state-of-the-art in model-based design at various steps of the design process (model refinement, test, code generation, ...) and at various technical and formal levels (thesis Richa), but also the definition of modelling languages. These contributions on model-driven engineering have been acknowledged by the scientific community, e.g., through a Best Paper Award at ICMT 2015

RAMSES allows to automatically derive implementation models from high-level design models (thesis Cadoret) in order to validate low-level software implementations, to analyse the availability as well as the schedulability of mixed-criticality applications (thesis Medina), or, even, to explore the design space of implementations through model transformation (thesis Rahmoun). Parts of this work have been carried out with industrial partners such as Alstom in the context of the IRT SystemX as well as the chair « Ingénierie de Systèmes Complexes » with academic partners from École Polytechnique and ENSTA ParisTech. A follow-up project ISC recently started (thesis Hassine) aiming at managing uncertainty in model-based design exploration. The RAMSES tool has also been selected as a showcase project by Institute.

Safety and Security Systems

Following up the project ELA, the project CTI (thesis Oudot) is currently starting, again in the context of the IRT SystemX, and allowed to establish a new collaboration with A. Easwaran (NTU, Singapore). This work aims at addressing security issues that may impact safety and realiability issues by improving the critical system design process.

Projects and PhD thesis


Teaching Activities

Real-time Embedded Systems

Concurrent Programming

Java Programming (first year)

System Programming (first year)


Administration Activities

Télécom ParisTech

Paris Saclay University