Safe and Secure Hardware (SSH) Team
COMELEC Department Telcom-ParisMy research is relevent to microarchitectural of intel x86, ARM, RISC-V. My mission is to harden open Architectures especially against microarchitectural leaks and active faults. We combine theory and practice across formal methods, simulation in gem5, and hardware prototyping. We are part of COMELEC in Telecom Paris, France. We advance the state of the art in microarchitectural security, side-channel & fault attack resistance, and trusted RISC-V SoC design with a focus on reproducible, open research.
We organize our work across the following themes.
Cache/branch leaks, transient execution, timing/power channels, and robust countermeasures.
Virtual and AI Based Platforms for Vulnearability Assesments, Embedded Security
Feature engineering, explainability (XAI), and robust ML for safety-critical domains.
Research: RISC-V security, microarchitectural leakage, formal verification, and secure SoC design.
Selected recent papers. For a full list, see Google Scholar.
@INPROCEEDINGS{10871078, author={Awais, Muhammad and Mushtaq, Maria and Naviner, Lirida and Bruguier, Florent and Yahya, Jawad Haj and Benoit, Pascal}, booktitle={2024 International Workshop on Rapid System Prototyping (RSP)}, title={Decoding Attack Behaviors by Analyzing Patterns in Instruction-Based Attacks using gem5}, year={2024}, volume={}, number={}, pages={1-6}, keywords={Reduced instruction set computing;Embedded systems;Hardware security;Conferences;Vectors;Pattern recognition;Decoding;Reliability;Optimization;Hardware Security;Embedded Systems;Hardware Attacks;Attacks Simulation;Attacks Patterns}, doi={10.1109/RSP64122.2024.10871078}}
We welcome applicants passionate about RISC-V hardware security.
Topics: side-channel analysis, transient execution defenses, secure RTL design. Start: [Month Year].
Apply via EmailHands-on work with FPGA prototypes, glitching setups, and measurement-based evaluation.
Contact UsHighlights from the lab.
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