Maria Mushtaq

Safe and Secure Hardware (SSH) Team

COMELEC Department Telcom-Paris

Illustration: research concept

About the me

My research is relevent to microarchitectural of intel x86, ARM, RISC-V. My mission is to harden open Architectures especially against microarchitectural leaks and active faults. We combine theory and practice across formal methods, simulation in gem5, and hardware prototyping. We are part of COMELEC in Telecom Paris, France. We advance the state of the art in microarchitectural security, side-channel & fault attack resistance, and trusted RISC-V SoC design with a focus on reproducible, open research.

Research Areas

We organize our work across the following themes.

Microarchitectural Attacks & Defenses

Cache/branch leaks, transient execution, timing/power channels, and robust countermeasures.

  • x86
  • RISC-V
  • ARM
#SideChannel #TransientExec
Virtual Platforms for Security Assesments

Virtual and AI Based Platforms for Vulnearability Assesments, Embedded Security

  • gem5
#gem5
AI based Hardware Security

Feature engineering, explainability (XAI), and robust ML for safety-critical domains.

  • Machine Learning Based
#RobustML

People

Research: RISC-V security, microarchitectural leakage, formal verification, and secure SoC design.

Group Leader
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Dr. Maria Mushtaq

Assistant Professor, COMELEC

Research: Hardware Security, Embedded Systems, ML, Side Channels Attacks at Telecom Paris.

Students & Researchers
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Muhammad AWAIS
PhD Student
Working on gem5 assisted hardaware accelorator
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Nathanael SIMON
PhD Student
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Mahreen Khan
PhD Student
HarPerformance
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Muhammad HASSAN
PhD Student
Former Students
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Muhammad AWAIS
PhD Student
Working on gem5 assisted hardaware accelorator

Latest Publications

Selected recent papers. For a full list, see Google Scholar.

  1. Decoding Attack Behaviors by Analyzing Patterns in Instruction-Based Attacks using gem5
    Muhammad Awais, Maria Mushtaq, Lirida Naviner, Florent Bruguier RSP, 2024
    PDF BibTeX
                @INPROCEEDINGS{10871078,
      author={Awais, Muhammad and Mushtaq, Maria and Naviner, Lirida and Bruguier, Florent and Yahya, Jawad Haj and Benoit, Pascal},
      booktitle={2024 International Workshop on Rapid System Prototyping (RSP)}, 
      title={Decoding Attack Behaviors by Analyzing Patterns in Instruction-Based Attacks using gem5}, 
      year={2024},
      volume={},
      number={},
      pages={1-6},
      keywords={Reduced instruction set computing;Embedded systems;Hardware security;Conferences;Vectors;Pattern recognition;Decoding;Reliability;Optimization;Hardware Security;Embedded Systems;Hardware Attacks;Attacks Simulation;Attacks Patterns},
      doi={10.1109/RSP64122.2024.10871078}}
    
        
    2025
  2. Fault Injection Resilience for Open RISC-V SoCs
    Muhammad Awais, Maria Mushtaq, Lirida Naviner, Florent Bruguier RTNS, 2025
    2025

Open Positions

We welcome applicants passionate about RISC-V hardware security.

Topics: side-channel analysis, transient execution defenses, secure RTL design. Start: [Month Year].

Apply via Email

Hands-on work with FPGA prototypes, glitching setups, and measurement-based evaluation.

Contact Us

News & Events

Highlights from the lab.

eurotech visit
Visit
Visiting Researcher Programme Accepted Eurotech

Aug 2025 — Accepted at HOST.

iolts
Paper
Side Channel attack detection using gem5 and Machine Learning: A Case Study on Fault-based Attacks in RISC-V

July 2025 — IOLTs, ISCHIA, ITALY.

positions
Hiring
We are Hiring, Positions open in the team

Aug 2025.

Contact

Reach out for collaborations, positions, or media.

Place Marguerite Perey
COMELEC, Telecom Paris
Cs 20031
Palaiseau, France

Email

@Maria_Mushtaq_

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