1. Objectives

We will design a DES Data Encryption Standard accelerator able to perform en encryption of bloc of data stored in memory using DMA transferts.

The DES reference function as the following interface:

  • 64 bits input encryption key

  • 64 bits input clear text

  • 64 bits output encrypted text

The behavior of the wanted component should be as follows:

  • The NiosII cpu will transfert to the DES component informations such as

    • the encryption key,

    • the start address on the clear message stored in memory

    • the length of the message (number of 64bit words)

    • the start address of the encrypted message.

  • Then the NiosII cpu starts the component and waits for completion.

The component should perform direct memory access for the memory I/Os.

2. The initial archive

Download the tar archive containing some initial files and directories. Extract the files in a work directory. After extraction you should have several directories related to each step of the lab.

3. You work

  • You have access to all documentations (see lab2).

You should be able to setup a component with the following behavior:

  • Act as an Avalon Slave component (see hls_avalon_slave_component in the documentation).

  • Act as an Avalon MM master (see Avalon Memory-Mapped Master Interfaces in the documentation).

The you should be able to setup a program, running on the NiosII processor used to test the componenent.