If the input of an inverter goes from 0 to 1, its output will go from 1 to 0. This transition is not instantaneous.

The delay from the input change to the output change is called propagation delay (t_p in the previous figure).

Let’s try to quantify this delay and to link it to the MOS characteristics.

Both nMOS and pMOS transistors act as voltage controlled current sources. The saturation current that flows between drain and source depends on the voltage applied between the gate and the source.

I_{ds} = F(V_{gs})

In the following, we will give more details about this relation and how it depends on the physical dimensions of the MOS transistor.

The electrical characteristics of the nMOS transistor shows that there is a quadratic relation between the Drain-Source current and the gate voltage.

K_n is a proportionality factor that depends on the size and the physics of the transistor.

K_n = \frac{1}{2} \mu_{0N} \cdot C'_{ox} \frac{W_N}{L_N}

• \mu_{0N} electron mobility in the semiconductor
• C'_{ox} gate capacitance per unit of surface
• W_N, L_N width and length of the gate

The K_n constant links the saturation current to the physical dimensions of the transistor and the nature on the material.

To increase the saturation current, we will need wider (W_n \nearrow), shorter (L_n \searrow), transistors with smaller gate capacitance.

For digital logic gate, the transistor can be considered at two distinct states:

• as an open switch, when the Gate voltage (V_{gs}) is null, the Drain-source voltage is V_{dd}, and the Drain-Source current is null,
• or as a closed switch, when the Gate voltage is V_{dd} (the power supply) and the Drain-source tension is null.

During the transition from the open to the closed state, we will assume that the current that flows between the Drain and the Source is equal to the saturation current I_{DSmax} as we will see in the next section.

Note that this model is a rather simplified model of a MOS transistor used here to understand the principles involved in the propagation delay in digital gates. More complex and complete models exist to describe more accurately MOS electrical characteristics. Those models are generally used for the electrical simulation of electronic designs.

The input of CMOS gates, and the connections between them, can be considered as capacitors. Multiple CMOS gates are seen at the output of a gate as an equivalent load capacitor. In addition, internal capacitances in the CMOS gate should be considered.

The load capacitor could thus be expressed as the sum of two terms:

C_L = C_i + C_e

• C_i the gate intrinsic capacitor
• C_e the equivalent capacitor due to the load

We consider the following initial state: - i = 0 and o = 1

Which means that the voltage at the gate output V_c = V_{dd}.

If we change the state of the input (i=1), the nMOS transistor will behave as a closed switch and the load capacitance C_L will discharge through it.

The discharge current:

I_{C_{dis}} = C_{L} \frac{d V}{dt}

Can be considered (as a first order approximation) as constant and equal to I_{DSmax}.

The propagation delay is thus:

t_p = C_L \frac{\Delta V}{I_{DSmax}} = C_L \frac{\frac{V_{dd}}{2}}{K_n\cdot(V_{dd}-V_t)^2}

Finally, we can express this delay with the following formula:

t_p = t_{p0} + d_{tp} \cdot C_e

With:

• d_{tp} = \frac{V_{dd}}{2K_n(V_{dd}-V_t)^2} the capacitive dependence
• t_{p0} = d_{tp}\cdot C_i intrinsic gate propagation delay

Generally, the characterization of standard gates (standard-cells) is done by the manufacturer. This characterization is performed by simulating the electrical behaviour of the gates. The simulation models will be based on experimental measurements done on some simple test devices.

Tables describing the propagation delays (intrinsic and extrinsic) are thus available to designers to evaluate the propagation delay of complex operators without the need to perform electrical simulations.

Note that for modern technologies, the propagation models are more complex, and will have more parameters to express more dependencies to temperature, rise time…

For the Full-Adder, we can compute the propagation delay from the inputs a_i, b_i, c_i to the outputs s_i and c_{i+1}.

For the full operator, we must consider the longest propagation path for all possible inputs values. This path starts at the input of the LSB Full-Adder and goes all the way to the MSB Full-Adder.

The propagation delay of the complete adder can be expressed as a function of the propagation delay of a single Full-Adder and the width of (number of bits) of the addition.

t_p \simeq N \times t_{pFA}

NOTE The longest propagation path in a combinational operator is called the critical path. As we do not know the values at the input of the operators at run time, we must wait for this delay before considering the values at the output as valid.

• S lower 4-bit sum
• S_0 higher 4-bit half sum with a 0 input carry
• S_1 higher 4-bit half sum with a 1 input carry
• The output multiplexors select between the two MSB halves sums depending on the output carry from the lower half sum.

This operator output is always the sum of the two 8-bit inputs. It is an 8-bit adder!

This implementation is called CSA (Carry Select Adder) because the result of the MSB half is selected depending on the value of the carry from the lower part.

As the two MSB halve sums are performed in parallel and do not wait for the carry propagation from thee lower half sum, the global propagation delay is close to the propagation delay of the half sum.

Here:

t_p \simeq 8/2 \times t_{pFA}

The CSA architecture allows the reduction of the propagation delay at the cost of higher hardware complexity.

As the propagation occurs concurrently in all possibles paths, we must not consider each adder independently. We must decompose each operator into elementary combinational operators to find all propagation paths.

We can show, for this example, that the propagation delay is close to the propagation delay of a single adder.