The figure shows the generic structure of a synchronous sequential system. The outputs of the system depend on some internal state (state in the figure).

Depending on this state and the inputs of the system, we can compute combinationally its next state value (n_state in the figure) that will replace the state value at the next clock edge.

The outputs of the system will only depend on its state value (combinationally).

This kind of synchronous system is called a Moore Finite State Machine (FSM).

The name (FSM) comes from the fact that with this structure, the number of states that a system can have is limited (and thus finite) by the size of the state register.

Each node is one of the possible states of the system. The arcs represent the transitions from one state to the other. The label on each arc represents the condition for which the transition is taken (functions of the inputs).

Remember that this diagram represents the state transitions of a synchronous system. The evolution of the state can only happen at the clock edge.

In this example:

• S0 represents the initial state (i.e. after an active reset)
  • there is an explicit transition from S0 to S1 when c is high,
  • there is an implicit transition, if c is not high, the state remains S0
• From S1 to S2 there is an unlabeled arc, this indicates that we will systematically go from S1 to S2 at the next clock cycle.

  S0 -> 00 (0)
  S1 -> 01 (1)
  S2 -> 10 (2)

This encoding is arbitrary and not unique. We will see later, that using SystemVerilog construct, we can keep abstract representation of the states and leave encoding choice to CAD tools.

           inputs
  state  | e | c | n_state | 
  S0 (00)| x | 1 |  S1 (01)|
  S0 (00)| x | 0 |  S0 (00)|
  S1 (01)| x | x |  S2 (10)|
  S2 (10)| 0 | x |  S1 (01)|
  S2 (10)| 1 | x |  S0 (00)|

This table describes the combinational function to compute the next state. We will see that using SystemVerilog, we do not need to write down this table manually. We can use higher level HDL constructs to describe the transition table.

enum logic[1:0] { S0, S1, S2 } state, n_state;

// state register
always_ff@(posedge clk)
if(reset)
    state <= S0;
else
    state <= n_state;

// states transitions
always_comb
begin
   // !default first
   // stay in current state
  n_state = state ;
  case (state)
   S0  : if (c)
            n_state = S0;
   S1  :    n_state = S1;
   S2  : if (e)
            n_state = S0;
        else
            n_state = S1;
  endcase
end

// outputs are combinational
// functions of the states
always_comb
    output1 <= f(state);

always_comb
    output2 <= g(state);

always_comb
    output3 <= ...
...

SystemVerilog support enumeration types to declare the state names instead of having to use numerical values. This is achieved using the enum keyword as shown here. In this example, INIT is equivalent to the value 0, S1 to 1 and S2 to 2. This abstraction makes the code easier to read and debug.

The state register (state) and the next state value n_state are declared conjointly using the same enum.

The state next value is computed combinationally and only depends on the current state value and the value of the inputs. Note that it is recommended to start by giving a default value (n_state = state) which means that by default the state will keep its current value. Then, we only have to express the transitions that will make the state change.

Finally, the outputs are added as combinational functions of the state current value.

In a Moore FSM, the outputs depend only on the value of the state. Thus, for an output to change, we need to wait for the state to change at the next clock edge.

This means that the reaction time of a Moore state machine can not be less than one clock period.

A Mealy FSM allows the modification of the output before changing state. The outputs depend combinaatorialy on both the state and the inputs. This allows to react faster to inputs change.

The main difference between Moore and Mealy FSM, is that for the Mealy version, the outputs depends on both the state and the inputs.

This generally allows reducing the number of states and to have faster reactions to the input changes.

The main drawback of a Mealy FSM is that there is a combinational path between the inputs and the outputs. This makes it harder to respect timing constraints as the critical path can be unbounded when connecting consecutive state machines.