The transformation of the HDL description into a list of interconnected gates (netlist) is called Logical Synthesis.

As HDLs have been designed for both Simulation and Synthesis, only a subset of these languages can to represent digital hardware. For example, it is useful to have commands to print messages during simulation, but those commands can not be magically transformed into a set of logic gates. This subset is called synthetisable subset of the language.

Also, the intent of the designer is very important. You must think hardware and not software, have an idea of the architecture that you want to get and only use the HDL to describe it.

There are two commonly used HDL with equivalent functionalities (but very different syntaxes) VHDL and Verilog/SystemVerilog. In this course, we will only use SystemVerilog, but the concepts can be easily transposed to VHDL.

Modules are declared with the module keyword. The list of inputs and outputs of the modules (its interface) must also be declared.

• inputs are declared using the input keyword
• outputs are declared using the output keyword

NOTE that no SystemVerilog code must appear outside a module.

• Multi-bit buses

For multi-bit buses, the square brackets [...] indicate the range.

For example:

input [3:0] A

A is a 4-bit input bus composed of a[3],a[2],a[1] and a[0] bits. a[3] being the most significant bit, and a[0] the least significant one.

A can also be interpreted as a 4-bit unsigned number.

NOTE Continuous assignment are not simple assignment similar to what can be found in standard programming languages. In SystemVerilog, continuous assignment are evaluated continuously and in a concurrent manner. They represent the behaviour of a combinational operator/gate.

SystemVerilog operators are generally similar to the ones that you can find in the C programming language.

The must usual are:

• binary operators

• arithmetic:

• comparison

• logical

• ternary

When instantiating a submodule we must connect its inputs and outputs to signals in the upper module.

Describing the modules hierarchy by instantiating submodules is called structural description.

Signals declared with the wire keyword can be used to connect the inputs/outputs of a module or as the output of continuous assignments.

• Example:

module FA2(
          input a,
          input b,
          input ci,
          output s,
          output co );

   wire hs, hc;

   assign hs = a ^ b;
   assign hc = a & b;

   assign s = hs ^ ci;
   assign co = hc |  hs & ci;

endmodule

module ADDER(
          input [3:0] a,
          input [3:0] b,
          input ci,
          output [3:0] s,
          output co );

   wire[4:0] c;

   FA FA_0(.a(a[0]), .b(b[0]), .ci(c[0]), .s(s[0]), .co(c[1]));
   FA FA_1(.a(a[1]), .b(b[1]), .ci(c[1]), .s(s[1]), .co(c[2]));
   FA FA_2(.a(a[2]), .b(b[2]), .ci(c[2]), .s(s[2]), .co(c[3]));
   FA FA_3(.a(a[3]), .b(b[3]), .ci(c[3]), .s(s[3]), .co(c[4]));

   assign c[0] = ci;
   assign co = c[4];

endmodule

NOTE FOR LATER This example is given to illustrate structural description in SystemVerilog. For such simple combinational operator, it is recommended to use the arithmetic operators. The corresponding structure will be inferred by synthesis tools.

The 4-bit adder should have been written:

module ADDER(
          input [3:0] a,
          input [3:0] b,
          input ci,
          output [3:0] s,
          output co );

assign {co,s} = a + b + ci;

endmodule

In SystemVerilog {...} is the concatenation operator. Here, {co,s} is a 5-bit bus. The operator expansion rules of SystemVerilog will expand right-hand operators and the addition will be performed on 5-bit.

NOTE The logic type allows the declaration of variables while the wire type represents nets. Only variables can be modified within a process.

In old Verilog dialect, the logic type was called reg. SystemVerilog added the logic type as a replacement to avoid confusion with Registers (synchronous memorising elements of flip-flops) because we can also describe combinational logic with them.

To describe combinational logic we can use either always@(*) or always_comb. The first one was introduced in Verilog-2001 while the second was introduced later to allow the designer to express its intention. The two constructs can be considered equivalent (differences exist but are beyond what is presented here). They can be interpreted as always if the inputs change, recompute the outputs.

Processes allow the utilization of usual software control sequences (if...else, case…) to describe the behaviour of the combinational logic.

Note that we have declared o as an output logic to be able to modify it in a process.

• Numbers in SystemVerilog

In SystemVerilog you can specify the size (number of bits) and express numbers in different bases. The format is N'Bxxxx where N si the size in bits and B the base.

Examples: