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Florian Brandner Associate Professor (HDR) ACES Team LTCI Télécom Paris Institut Polytechnique de Paris |
Florian Brandner
Office 4D59
Télécom Paris
19, Place Marguerite Perey
91120 Palaiseau
France
+33 (0)1 75 31 97 74
florian.brandner (at) telecom-paris.fr
https://orcid.org/0000-0002-2493-7864
My curriculum vitae can be downloaded here.
I am member of the ACM and the HiPEAC network of excellence.
My current research topic is on compiler-backend optimizations for embedded processors, foremost VLIW-style architectures, in the context of real-time systems. In contrast to traditional compilation, the goal here is not to reduce the execution time of the average-case. Instead the worst-case execution time (WCET) is optimized. The main challenge is that during the compilation process it is not yet clear which code paths will actually be relevant for the WCET.
During a two-year stay in France at the COMPSYS Team of the ENS de Lyon, I have been working on traditional compilation, particularly on trying to exploit properties of Static Single Assignment form (SSA) in order to improve the compilation time and code quality of dynamic as well as static compilers.
Previously, I worked on processor description languages, where compiler components, cycle-accurate simulators, and even hardware models (VHDL) were derived from a given processor specification. The compiler generation is focused on the open source compiler infrastructure LLVM. The simulator uses a mixed approach based on interpretation and dynamic compilation via the LLVM JIT compiler. See my PhD thesis and the publications below for more details.
In general I'm interested in code generation techniques, register
allocation, instruction scheduling and instruction bundling for VLIW
architectures, as well as simulation techniques, such as dynamic binary
translation. Recently, I also found interest in problems related to
computing under timing constraints (real-time systems, etc.).
Système d'exploitation et langage C (INF104/SELC)
Lecturer: F. Brandner (Coordinator)
INFO Course Material
Projet de programmation (INF280)
Lecturer: A. Amarilli, E. Borde, B. Meyer, F. Brandner
INFO
Support d'exécution (SE201)
Lecturer: F. Brandner
INFO
Programmation concurrente (SE205)
Lecturer: L. Pautet, F. Brandner
INFO
Course Material
Systèmes Temps Réel Embarqués Critiques (SE301a/b or STREC for master SAR)
Lecturer: T. Robert, L. Pautet, M. Jan, E. Borde, F. Brandner
INFO (SE301a) and
INFO (SE301b)
Noyaux Temps Rèel (COMASIC906, Master COMASIC)
Lecturer: L. Pautet, M. Jan, E. Borde, F. Brandner
INFO
Systèmes Temps Réel Embarqués Critiques (SE751 of Mastère Spécialisé Systèmes Embarqués)
Lecturer: L. Pautet, E. Borde, F. Brandner
INFO
Programmation concurrente (SE745 of Mastère Spécialisé Systèmes Embarqués)
Lecturer: L. Pautet and F. Brandner (Coordinator)
INFO
Computer Organization and Architecture (SJTU-ParisTech, COA-CS450)
Lecturer: F. Brandner
INFO
Système d'exploitation et langage C (INF104/SELC)
Lecturer: F. Brandner (Group 2)
INFO Course Material
Support d'exécution (SE201)
Lecturer: Kameswar Vaddina and F. Brandner
INFO
Programmation concurrente (SE205)
Lecturer: L. Pautet, F. Brandner
INFO
Course Material
Programmation concurrente (SE745 of Mastère Spécialisé Systèmes Embarqués)
Lecturer: L. Pautet, F. Brandner
INFO
Architecture Matérielle des Ordinateurs (SJTU-ParisTech, CS443)
Lecturer: Kameswar Vaddina and F. Brandner
INFO
Projet de programmation (INF280)
Lecturer: A. Amarilli, E. Borde, B. Meyer, F. Brandner
INFO
Systèmes Temps Réel Embarqués Critiques (SE301a/b or STREC for master SAR)
Lecturer: T. Robert, L. Pautet, M. Jan, E. Borde, F. Brandner
INFO (SE301a) and
INFO (SE301b)
Noyaux Temps Rèel (COMASIC906, Master COMASIC)
Lecturer: L. Pautet, M. Jan, E. Borde, F. Brandner
INFO
Systèmes Temps Réel Embarqués Critiques (Mastère Spécialisé Systèmes Embarqués)
Lecturer: L. Pautet, E. Borde, F. Brandner
Project Assignment (Master SETI, M2)
Lecturer: F. Brandner
INFO
Projet d'application final (PROJ102)
Lecturer: F. Brandner
INFO
Projet d’Apprentissage Collaboratif Thématique (PACT)
Lecturer: F. Brandner
INFO
Support d'exécution (SE201)
Lecturer: Kameswar Vaddina and F. Brandner
INFO
Systèmes Temps Réel Embarqués Critiques (SE301b or STREC for master SAR)
Lecturer: T. Robert, L. Pautet, M. Jan, E. Borde, F. Brandner
INFO (SE301b)
Architecture Matérielle des Ordinateurs (SJTU-ParisTech, CS443)
Lecturer: Kameswar Vaddina and F. Brandner
INFO
Projet de programmation (INF280)
Lecturer: A. Amarilli, E. Borde, B. Meyer, F. Brandner
INFO
Project Assignment (Master SETI, M2)
Lecturer: F. Brandner
INFO
Système d'exploitation et langage C (INF104/SELC)
Lecturer: F. Brandner (Group 1 and 2)
INFO Course Material
Projet d’Apprentissage Collaboratif Thématique (PACT)
Lecturer: F. Brandner
INFO
Support d'exécution (SE201)
Lecturer: F. Brandner
INFO
Programmation concurrente (SE205)
Lecturer: L. Pautet, F. Brandner
INFO
Course Material
Systèmes Temps Réel Embarqués Critiques (SE301 or STREC for master SAR/SETI/COMASIC)
Lecturer: T. Robert, L. Pautet, M. Jan, E. Borde, F. Brandner
INFO (SETI/COMASIC)
Architecture Matérielle des Ordinateurs (SJTU-ParisTech, CS443)
Lecturer: F. Brandner
INFO
Projet de programmation (INF280)
Lecturer: A. Amarilli, B. Meyer, F. Brandner
INFO
Système d'exploitation et langage C (INF104/SELC)
INFO Supports
Projet d’Apprentissage Collaboratif Thématique (PACT)
Lecturer: F. Brandner
INFO
Support d'exécution (SE201)
Lecturer: T. Robert, F. Brandner
INFO Supports
Programmation concurrente (SE205)
Lecturer: L. Pautet, F. Brandner
INFO
Supports
Master SAR/COMASIC (INF940)
Lecturer: T. Robert, L. Pautet, M. Jan, E. Borde, F. Brandner
INFO
Architecture Matérielle des Ordinateurs (SJTU-ParisTech, AMO402)
Lecturer: F. Brandner
INFO
Parallélisme (ENSTA, IN203)
Professor: F. Brandner, P. Kestener
INFO
Supports
Parallélisme (IN203)
Professor: F. Brandner, P. Kestener
INFO
Compilation et Optimisations de code (B6-4)
Professor: B. Monsuez, F. Brandner
INFO
Algorithmique et Programmation (en Python) (IN101)
Professor: F. Stulp, F. Brandner, A. Gepperth
INFO
Projet informatique (IN104)
Professor: F. Stulp
INFO
Systèmes Èlectroniques Embarqués (ES430)
Professor: Omar Hammami
Exercises
INFO
Systèmes d'exploitation (IN102)
Professor: Bertrand Collin
INFO
| Google Scholar | DBLP |
Procede de calcul d’un pire temps de transmission, programme d’ordinateur et systeme informatique associes
Florient Champenois (Safran), Thierry Grandpierre (ESIEE), Florian Brandner
French Patent
Nov. 2023 (pending)
Time-division multiplexing method and circuit for concurrent access to a computer resource
Farouk Hebbache (CEA), Mathieu Jan (CEA), Florian Brandner, Laurent Pautet
US Patent App. 17/289,270
Dec. 2021 (pending)
Procede et circuit de multiplexage temporel d'acces concurrents a une ressource informatique
Farouk Hebbache (CEA), Mathieu Jan (CEA), Florian Brandner, Laurent Pautet
French Patent FR3087982B1
Oct. 2018 / Dec. 2020 (granted)
Designing Formally Verified Predictable Architectures
Lilia Rouizi, Mihail Asavoae(CEA LIST), Lionel Rieg (Verimag), Benjamin Binder and Florian Brandner (Télécom Paris)
CEA 2023-2026
Collaborative Action on Timing Interferences
Florian Brandner and Dominique Blouin (Télécom Paris), partners from CEA List, Inria Paris, Irisa, IRIT, IRT Saint-Exupery, LS2N, and Verimag
ANR 2022-2026
Secure Dynamic Real-Time Memory Hierarchy
Mihail Asavoae (CEA LIST), Abdelhafid El Ouardi (Université Paris-Saclay), Sumanta Chaudhuri, Florian Brandner, Felipe Lisboa, and Lirida Naviner (Télécom Paris)
DigiCosme 2020-2024
Real-Time System Design using Formal Verification of Temporal Predictability
Mathieu Jan, Benjamin Binder, Mihail Asavoae, Belgacem Ben Hedia (CEA LIST), and Florian Brandner (Télécom Paris)
CEA 2019-2022
Time-Predictable Cache Management for Real-Time Systems (TP-CoMFORT)
Mathieu Jan, Farouk Hebbache (CEA LIST), Florian Brandner, Laurent Pautet (Télécom ParisTech)
CEA 2016-2019
Automatic Frequency and Voltage Scaling of Programs (AAFUP)
Gérard Memmi (Télécom ParisTech), Pierre Jouvelot, Corinne Ancourt (Mines ParisTech), Florian Brandner
Intercarnot 2016-2019
Profiling Metrics and Techniques for the Optimization of Real-Time Programs (PM-TOP)
Florian Brandner, Mathieu Jan (CEA LIST), Albert Cohen (INRIA/ENS), and Amine Naji (ENSTA ParisTech)
Digiteo 2014-0741D, 2014-2017
Proceedings of the 18th International Workshop on Worst-Case Execution Time Analysis
Florian Brandner
Barcelona, Spain, 2018
OASIcs, LINK
Proceedings of the 11th Workshop on Optimizations for DSP and Embedded Systems
Florian Brandner, and Tom Vander Aa (Editors)
Orlando, FL, USA, 2014
ACM ICPS, 
LINK
Proceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems
Florian Brandner, and Tom Vander Aa (Editors)
Shenzhen, China, 2013
ACM ICPS, LINK
DSP Instruction Set Simulation
Florian Brandner, Nigel Horspool, and Andreas Krall
Handbook of Signal Processing Systems (2nd Edition),
S.S. Bhattacharyya, E.F. Deprettere, R. Leupers, and J. Takala (Editors)
Springer, 2013, INFO,
FULLTEXT,
CHAPTER
DSP Instruction Set Simulation
Florian Brandner, Nigel Horspool, and Andreas Krall
Handbook of Signal Processing Systems,
S.S. Bhattacharyya, E.F. Deprettere, R. Leupers, and J. Takala (Editors)
Springer, 2010, INFO,
FULLTEXT,
CHAPTER
A Formal Framework to Design and Prove Trustworthy Memory Controllers
Felipe Lisboa Malaquias, Mihail Asavoae, Florian Brandner
Real-Time Systems (TIME), Springer
online: 14. Nov. 2023, PDF
Formal Modeling and Verification for Amplification Timing Anomalies in the Superscalar TriCore Architecture
Benjamin Binder, Mihail Asavoae, Florian Brandner, Belgacem Ben Hedia, and Mathieu Jan
Journal on Software Tools for Technology Transfer (STTT), Springer
Volume 24(3): pages 415-440 (2022)
online: 8. Mar. 2022, PDF, DOI.
Precise, Efficient, and Context-Sensitive Cache Analysis
Florian Brandner
Real-Time Systems (TIME), Springer
Volume 58(1): pages 36-84 (2022)
online: 26. Jun. 2021, AAM*, PDF
* This is a post-peer-review, pre-copyedit version of an article published in the Real-Time Systems Journal. The final authenticated version is available online at: https://doi.org/10.1007/s11241-021-09372-5.
Work-Conserving Dynamic Time-Division Multiplexing for Multi-Criticality Systems
Farouk Hebbache, Florian Brandner, Mathieu Jan, and Laurent Pautet
Real-Time Systems (TIME), Springer
Volume 56(2): 124-170 (2020)
online: 29. Jul. 2019, AAM*, PDF
* This is a post-peer-review, pre-copyedit version of an article published in the Real-Time Systems Journal. The final authenticated version is available online at: https://doi.org/10.1007/s11241-019-09336-w.
Analysis of Preemption Costs for the Stack Cache
Amine Naji, Sahar Abbaspour, Florian Brandner, and Mathieu Jan
Real-Time Systems (TIME), Springer
Volume 54(3): 700-744 (2018)
online: 6. Feb. 2018, AAM*, PDF
* This is a post-peer-review, pre-copyedit version of an article published in the Real-Time Systems Journal. The final authenticated version is available online at: https://dx.doi.org/10.1007/s11241-018-9298-7.
Studying Optimal Spilling in the Light of SSA
Quentin Colombet, Florian Brandner, and Alain Darte
ACM Transactions on Architecture and Code Optimization (TACO), ACM
Volume 11(4): (2015), PDF
Refinement of Worst-Case Execution Time Bounds by Graph Pruning
Florian Brandner and Alexander Jordan
Computer Languages, Systems & Structures (COMLAN), Elsevier
Volume 40(3-4): 155-170 (2014)
online: 28. Sep. 2014, DOI
Criticality: Static Profiling for Real-Time Programs
Florian Brandner, Stefan Hepp, and Alexander Jordan
Real-Time Systems (TIME), Springer
Volume 50(3): 377-410 (2014)
online: 31. Oct. 2013, DOI
Elimination of Parallel Copies using Code Motion on Data Dependence Graphs
Florian Brandner and Quentin Colombet
Computer Languages, Systems & Structures (COMLAN), Elsevier
Volume 39(1): 25-47 (2013)
online: 5. Oct. 2012, DOI
Automatic Generation of Compiler Backends
Florian Brandner, Viktor Pavlu, and Andreas Krall
Software: Practice and Experience (SPE), John Wiley & Sons, Ltd
Volume 43(2): 207-240 (2013)
online: 16. Jan. 2012, DOI
Leveraging Reusable Code and Proofs to Design Complex DRAM Controllers - A Case Study
Felipe Lisboa, Mihail Asavoae, and Florian Brandner
Euromicro Digital System Design Conference (DSD)
France, 2024, IEEE, 
PDF*
too appear
* This is a post-peer-review version of a paper published at DSD'24. The final version will soon be available from IEEE.
Experimental Assessment and Biaffine Modeling of the Impact of Ambient Temperature on SoC Power Requirements
Kameswar Rao Vaddina, Florian Brandner, Gerard Memmi, and Pierre Jouvelot
International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)
Grece, 2024, Springer, AAM*
too appear
* This is a post-peer-review, pre-copyedit version of an article published in the proceedings of SAMOS'24. The final authenticated version will soon be available from Springer.
Multi-Criteria Optimization of Distributed Real-Time Network Topologies
Florient Champenois, Abraham Suissa, Laurent George, Thierry Grandpierre, Etienne Borde, and Florian Brandner
International Symposium on Real-Time Distributed Computing (ISORC)
Tunisia, 2024, IEEE, DOI, PDF*
* This is a post-peer-review version of a paper published at ISORC'24. The final version is available from IEEE:
979-8-3503-7128-4/24/31.00 ©2024IEEE
DOI: 10.1109/ISORC61049.2024.10551327.
From the Standards to Silicon: Formally Proved Memory Controllers
Felipe Lisboa, Mihail Asavoae, and Florian Brandner
International NASA Formal Methods Symposium (NFM)
USA, 2023, Springer, DOI, AAM*,
* This is a post-peer-review, pre-copyedit version of an article published in the proceedings of the International NASA Formal Methods Symposium. The final authenticated version is available online at: https://doi.org/10.1007/978-3-031-33170-1_18.
The Role of Causality in a Formal Definition of Timing Anomalies
Benjamin Binder, Mihail Asavoae, Florian Brandner, Belgacem Ben Hedia, and Mathieu Jan
International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)
Taiwan, 2022, PDF*, DOI
* This is a post-peer-review version of a paper published at RTCSA'22. The final version is available from IEEE:
2325-1301/22/$31.0 ©2022 IEEE
DOI: 10.1109/RTCSA55878.2022.00016.
A Coq Framework for More Trustworthy DRAM Controllers (Best Paper Award)
Felipe Lisboa Malaquias, Mihail Asavoae, and Florian Brandner
International Conference on Real-Time and Network Systems (RTNS)
Paris, 2022, PDF
Is This Still Normal? Putting Definitions of Timing Anomalies to the Test
Benjamin Binder, Mihail Asavoae, Belgacem Ben Hedia, Florian Brandner, and Mathieu Jan
International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)
South Korea, 2021, PDF*, DOI
* This is a post-peer-review version of a paper published at RTCSA'21. The final version is available from IEEE:
978-1-6654-4188-9/21/$31.00 ©2021 IEEE
DOI: 10.1109/RTCSA52859.2021.00024.
Scalable Detection of Amplification Timing Anomalies for the Superscalar TriCore Architecture
Benjamin Binder, Mihail Asavoae, Florian Brandner, Belgacem Ben Hedia, and Mathieu Jan
International Conference on Formal Methods for Industrial Critical Systems (FMICS)
Vienna, Austria, 2020, DOI
Precise and Efficient Analysis of Context-Sensitive Cache Conflict Sets (Best Paper Award)
Florian Brandner
International Conference on Real-Time and Network Systems (RTNS)
Paris, France, 2020, PDF, Youtube Video
Arbitration-Induced Preemption Delays
Farouk Hebbache, Florian Brandner, Mathieu Jan, and Laurent Pautet
Euromicro Conference on Real-Time Systems (ECRTS)
Stuttgart, Germany, 2019, PDF
Shedding the Shackles of Time-Division Multiplexing (Outstanding Paper Award)
Farouk Hebbache, Mathieu Jan, Florian Brandner, and Laurent Pautet
Real-Time Systems Symposium (RTSS)
Nashville, USA, 2018, DOI
Experimental Energy Profiling of Energy-Critical Embedded Applications (Best Paper Award)
Kameswar Rao Vaddina, Florian Brandner, Gerard Memmi, and Pierre Jouvelot
Symposium on Green Networking and Computing (SGNC) part of SoftCOM 2017
Split, Croatia, 2017, DOI
Efficient Context Switching for the Stack Cache: Implementation and Analysis (Outstanding Paper Award)
Sahar Abbaspour, Florian Brandner, Amine Naji, and Mathieu Jan
23th International Conference on Real-Time and Network Systems (RTNS)
Lille, France, 2015, PDF
Splitting Functions into Single-Entry Regions
Stefan Hepp and Florian Brandner
International Conference on Compilers, Architecture, and Synthesis for
Embedded Systems (CASES)
New Delhi, India, 2014, PDF
A Loosely Synchronizing Asynchronous Router for TDM-Scheduled NOCs
Ioannis Kotleas, Dean Humphreys, Rasmus Bo Sørensen, Evangelia Kasapaki, Florian Brandner, and Jens Sparsø
International Symposium on Networks-on-Chip (NOCS)
Ferrara, Italy, 2014, DOI
Static Analysis of Worst-Case Stack Cache Behavior
Alexander Jordan, Florian Brandner, and Martin Schoeberl
21th International Conference on Real-Time and Network Systems (RTNS)
Sophia-Antipolis, France, 2013, PDF
Static Profiling of the Worst-Case in Real-Time Programs (Best Paper Award)
Florian Brandner, Stefan Hepp, and Alexander Jordan
20th International Conference on Real-Time and Network Systems (RTNS)
Pont-à-Mousson, France, 2012, PDF
Static Routing in Symmetric Real-Time Network-on-Chips
Florian Brandner and Martin Schoeberl
20th International Conference on Real-Time and Network Systems (RTNS)
Pont-à-Mousson, France, 2012, PDF
A Statically-Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time Systems
Martin Schoeberl, Florian Brandner, Evangelia Kasapaki, and Jens Sparsø
6th International Symposium on Networks-on-Chip (NOCS)
Kongens Lyngby, Denmark, 2012, DOI
Copy Elimination on Data Dependence Graphs
Florian Brandner and Quentin Colombet
27th Symposium On Applied Computing (SAC-PL)
Riva del Garda, Italy, 2012, PDF
A Non-Iterative Data-Flow Algorithm for Computing Liveness Sets in Strict SSA Programs
Benoit Boissinot, Florian Brandner, Alain Darte, Benoît Dupont De Dinechin, and Fabrice Rastello
International Symposium on Programming Languages and Systems (APLAS)
Kenting, Taiwan, 2011, DOI
Studying Optimal Spilling in the Light of SSA
Quentin Colombet, Florian Brandner, and Alain Darte
International Conference on Compilers, Architecture, and Synthesis for
Embedded Systems (CASES)
Taipei, Taiwan, 2011, PDF
Execution Models for Processors and Instructions
Florian Brandner, Viktor Pavlu, and Andreas Krall
28th Norchip Conference
Tampere, Finland, 2010
SPUR: A Trace-Based JIT Compiler for CIL
Michael Bebenita, Florian Brandner, Manuel Fahndrich, Francesco Logozzo, Wolfram Schulte, Nikolai Tillmann, and Herman Venter
International Conference on Object Oriented Programming Systems Languages and Applications (OOPSLA)
Reno, USA, October, 2010, PDF
Completeness of Automatically Generated Instruction Selectors
Florian Brandner
21st International Conference on Application-specific Systems, Architectures and Processors (ASAP)
Rennes, France, July, 2010, DOI
RTTM: Real-Time Transactional Memory
Martin Schoeberl, Florian Brandner, and Jan Vitek
25th Symposium On Applied Computing (SAC-RTS)
Sierre, Switzerland, March, 2010, PDF
Stack Allocation of Objects in the Cacao Virtual Machine
Peter Molnar, Andreas Krall, and Florian Brandner
7th International Conference on the Principles and Practice of Programming in Java (PPPJ)
Calgary, Canada, August, 2009, PDF
Embedded JIT Compilation with CACAO on YARI
Florian Brandner, Martin Schoeberl, and Tommy Thorn
12th IEEE International Symposium on Object/component/service-oriented Real-time distributed Computing (ISORC)
Tokyo, Japan, March, 2009, DOI
Generalized Instruction Selection using SSA-Graphs
Dietmar Ebner, Florian Brandner, Bernhard Scholz, Andreas Krall, Peter Wiedermann, and Albrecht Kadlec
ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)
Tucson, USA, June, 2008, PDF
Compiler Generation from Structural Architecture Descriptions
Florian Brandner, Dietmar Ebner, and Andreas Krall
International Conference on Compilers, Architecture, and Synthesis for
Embedded Systems (CASES)
Salzburg, Austria, October, 2007, PDF
Effective Compiler Generation by Architecture Description
Stefan Farfeleder, Andreas Krall, Edwin Steiner, and Florian Brandner
ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)
Ottawa, Canada, June, 2006, PDF
Dynamic Arbitration of Memory Requests with TDM-like Guarantees
Farouk Hebbache, Mathieu Jan, Florian Brandner and Laurent Pautet
Workshop on Compositional Theory and Technology for Real-Time Embedded Systems (CRTS)
Paris, France, 2017, PDF
Worst-Case Execution Time Analysis of Predicated Architectures
Florian Brandner and Amine Naji
Workshop on Worst-Case Execution Time Analysis (WCET)
Dubrovnik, Croatia, 2017, PDF
Eager Stack Cache Memory Transfers
Amine Naji and Florian Brandner
Workshop on Worst-Case Execution Time Analysis (WCET)
Toulouse, France, 2016, PROC, PDF
A Comparative Study of the Precision of Stack Cache Occupancy Analyses
Amine Naji and Florian Brandner
Junior Researcher Workshop on Real-Time Computing (JRWRTC)
Lille, France, 2015, PROC, PDF
Alignment of Memory Transfers of a Time-Predictable Stack Cache
Sahar Abbaspour and Florian Brandner
Junior Researcher Workshop on Real-Time Computing (JRWRTC)
Versailles, France, 2014, PROC, PDF
Lazy Spilling for a Time-Predictable Stack Cache: Implementation and Analysis
Sahar Abbaspour, Alexander Jordan, and Florian Brandner
Workshop on Worst-Case Execution Time Analysis (WCET)
Madrid, Spain, 2014, PDF
A Time-predictable Stack Cache
Sahar Abbaspour, Florian Brandner, and Martin Schoeberl
Workshop on Software Technologies for Embedded and Ubiquitous Systems (SEUS)
Paderborn, Germany, 2013, PDF
Studying Spilling in the Light of SSA
Quentin Colombet, Florian Brandner, and Alain Darte
Workshop on Compilers for Parallel Computing (CPC)
Padova, Italy, 2012
Modeling Application-Specific Processors for the Use in Cyber-Physical Systems
Florian Brandner, Viktor Pavlu, and Andreas Krall
Workshop on Software Language Engineering for Cyber-physical Systems (WS4C)
Berlin, Germany, October, 2011
Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach
Martin Schoeberl, Pascal Schleuniger, Wolfgang Puffitsch, Florian Brandner,
Christian W. Probst, Sven Karlsson, and Tommy Thorn
Workshop on Practice, Predictability and Performance in Embedded Systems (PPES)
Grenoble, France, March, 2011, PDF
Automatic Tool Generation from Structural Processor Descriptions
Florian Brandner
15th Biennial Workshop on Programmiersprachen und Grundlagen der Programmierung (KPS)
Maria Taferl, Austria, October, 2009,
PDF
Precise Simulation of Interrupts using a Rollback Mechanism
Florian Brandner
12th International Workshop on Software and Compilers for Embedded Systems (SCOPES)
Nice, France, April, 2009, PDF
Completeness of Instruction Selector Specifications with Dynamic Checks
Florian Brandner
8th International Workshop on Compiler Optimization Meets Compiler Verification (COCV)
York, England, 2009
Fast and Accurate Simulation using the LLVM Compiler Framework
Florian Brandner, Andreas Fellnhofer, Andreas Krall, and David Riegler
1st Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO)
Paphos, Cyprus, January, 2009,
PDF
Leveraging Predicated Execution for Multimedia Processing
Dietmar Ebner, Florian Brandner, and Andreas Krall
Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia)
Salzburg, Austria, October, 2007
Static Verification of Global Heap References in Java Native Libraries
Andreas Krall, Christian Thalinger, Dietmar Ebner, and Florian Brandner
Workshop on Semantics, Program Analysis, and Computing Environments for Memory Management (SPACE)
Charleston, USA, January, 2006
Subgraph-Based Refinement of Worst-Case Execution Time Bounds
Florian Brandner and Alexander Jordan
ENSTA Technical Report, 00978015
Palaiseau, France, April, 2014,
PDF
INFO
Parallel Copy Elimination on Data Dependence Graphs
Florian Brandner and Quentin Colombet
INRIA Technical Report, RR-7535
Lyon, France, September, 2011,
PDF
INFO
Computing Liveness Sets for SSA-Form Programs
Florian Brandner, Benoit Boissinot, Alain Darte, Benoît Dupont De Dinechin, and Fabrice Rastello
INRIA Technical Report, RR-7503
Lyon, France, January, 2011,
PDF
INFO
SPUR: A Trace-Based JIT Compiler for CIL
Michael Bebenita, Florian Brandner, Manuel Fahndrich, Francesco Logozzo, Wolfram Schulte, Nikolai Tillmann, and Herman Venter
Technical Report, Microsoft Research, MSR-TR-2010-27
Redmond, USA, March, 2010,
PDF
Embedded JIT Compilation with CACAO on YARI
Florian Brandner, Tommy Thorn, and Martin Schoeberl
Technical Report, Institute of Computer Engineering, Vienna University of Technology, RR 35/2008
Vienna, Austria, June, 2008,
PDF
INFO
D2.1 - Software Simulator of Patmos
Florian Brandner
Report of T-CREST Deliverable D2.1, 2012,
PDF
D5.2- Initial Compiler Version
Florian Brandner, Stefan Hepp, and Daniel Prokesch
Report of T-CREST Deliverable D5.2, 2012,
PDF
Compiler Backend Generation from Structural Processor Models
Florian Brandner
PhD thesis, Vienna University of Technology, 2009,
PDF
Efficient TDM-based Arbitration for Mixed-Criticality Systems on Multi-Cores
Scientific Day of IRT Saint Exupéry and GDR SOC2 (CNRS)
Novembre 16, 2018, Toulouse, France, PDF
INFO
Dynamic Arbitration of Memory Requests with TDM-like Guarantees
Seminar of the SEN and ACES teams of Télécom ParisTech
October 25, 2018, Paris, France
The Time-Predictable Processor Patmos and its Tool Chain
Seminar at the SEN team of the COMELEC Department of Télécom ParisTech
April 6, 2017, Paris, France
Time-predictable (stack) caches and their analysis
Meeting of the Working Group "Optimization of Real-Time Systems" (OVSTR)
October 15, 2015, Paris, France
Profiling Metrics and Techniques for the Optimization of Real-Time Programs: Analysis of Method Cache Extensions
DigiCosme Research Days
March 23, 2015, Gif-sur-Yvette, France
Lazy Spilling for a Time-Predictable Stack Cache: Implementation and Analysis
LRI, ParSys
Host: Christine Eisenbeis
October 14, 2014, Gif-sur-Yvette, France
Refinement of Worst-Case Execution Time Bounds by Graph Pruning
8th Meeting of the French Compilation Community
July 2, 2014, Nice, France
Refinement of Worst-Case Execution Time Bounds by Graph Pruning
VERIMAG
Host: Florence Maraninchi
April 3, 2014, Grenoble, France, PDF
Static Scheduling for Time-Predictable Networks-on-Chip
INRIA Rocquencourt (AOSTE)
Host: Dumitru Potop Butucaru
February 7, 2014, Rocquencourt, France, PDF
Static Analysis of Worst-Case Stack Cache Behavior
7th Meeting of the French Compilation Community
December 6, 2013, Dammarie Les Lys, France, PDF
Time-Predictable Communication in Networks-on-Chip
ENS de Lyon
Host: Alain Darte
February 14, 2013, Lyon, France, PDF
Static Scheduling for Time-Predictable Networks-on-Chip
Danmarks Tekniske Universitet, DTU Informatik
Host: Martin Schöberl
February 24, 2012, Copenhagen, Denmark, PDF
'Optimal' Spilling using Integer Linear Programming
Quentin Colombet, Florian Brandner, and Alain Darte
Vienna University of Technology
Host: Jens Knoop
Mai 27, 2011, Vienna, Austria, INFO
Compiler-driven Optimization of the Worst-Case Execution Time
Florian Brandner, and Alain Darte
Workshop Analyse to Compile, Compile to Analyse (ACCA)
April 3, 2011, Chamonix, France
Instruction Selection using PBQP
MEDIACOM Project Meeting
January 18, 2011, Grenoble, France
Completeness of Instruction Selectors
2nd Meeting of the Communauté Française de Compilation
December 9, 2010, Aussois, France, PDF
Automatic Compiler Generation from Structural Processor Models
Danmarks Tekniske Universitet, DTU Informatik
Host: Martin Schöberl
August 4, 2010, Copenhagen, Denmark, PDF
Automatic Compiler Generation from Structural Processor Models
Institut de Recherche en Informatique et Systèmes aléatoires, IRISA
Host: Steven Derrien
October 19, 2010, Rennes, France, PDF
MC-Member of the European COST Action Connecting Education and Research Communities for an Innovative Resource Aware Society (2020-)
Co-Cordinator of the DigiCosme Real-time Systems Working Group (OVSTR, 2015-2018)
Co-Cordinator of the French Compilation Group (2013-2017)
Organizing Committee:
RTSS 2017
ETR 2017
RTNS 2014
Co-organizer/Co-chair:
RTAS 2022 (PC co-chair track 1)
WCET 2018 (PC)
Euro-Par 2018 (global chair of topic 4)
Poster Chair of CGO 2016
9th Meeting of the French Compilation Community
ODES 2014
ODES 2013
Program Committee:
ECRTS 2024
RTAS 2024
SAC-CPS 2024
RTSS 2023
RTSS 2022,
WCET 2022
RTSS 2021,
ECRTS 2021,
DAC 2021,
RTAS 2021
DAC Late Breaking Results 2020,
DAC 2020 (track ESS1),
RTAS 2020
EWiLi 2019
RTNS 2019
WCET 2019
RTAS 2019
VECoS 2018,
RTNS 2018,
DATE 2018 (TPC of topic E2)
RTNS 2017,
SEAA 2017,
WCET 2017,
VECoS 2017,
DATE 2017 (TPC of topic E2)
VECoS 2016
RTNS 2016
SEAA 2016
ARCS 2016
CGO 2016
VECoS 2015,
RTNS 2015,
SEAA 2015,
ARCS 2015,
PECCS 2014,
PECCS 2013
Session Chair:
ECRTS 2018, CASES 2011
External Reviewer:
RSP 2018, DATE 2015, LCTES 2012, FPL 2012, WCET 2012, RTNS 2012, LPAR 2012, DATE 2012, CASES 2011, CC 2011, CGO 2011, PACT 2010, LCTES 2009, SCOPES 2008, PPPJ 2008, CASES 2008, PLDI 2006
Journal Reviewer:
ACM Transactions in Embedded Computing Systems (TECS), 2012 - 2024
Transactions on Computers (TC), 2021 - 2022
Real-Time Systems (TIME), 2014 - 2020
Journal of Systems Architecture (JSA), 2013 - 2020
ACM Transactions on Programming Languages and Systems (TOPLAS), 2018 - 2019
ACM Transactions on Architecture and Code Optimization (TACO), 2015 - 2017
ACM Transactions on Design Automation of Electronic Systems (TODAES), 2016 - 2017
International Journal of Critical Computer-Based Systems (IJCCBS), 2016
Journal of Cryptographic Engineering (JCEN), 2016
Science of Computer Programming (SCICO), 2016
Computing (COMP), 2013
Parallel Computing (PARCO), 2013
Software: Practice and Experience (SPE), 2012
EURASIP Journal on Embedded Systems (JES), 2011 - 2012
IEEE Transactions on Circuits and Systems for Video Technology (TCSVT), 2010
Shanghai Jiao Tong University-ParisTech Elite Institute of Technology (SPEIT)
Shanghai, China, 2015-2020
Lecturer of a course on computer architecture at SPEIT.
University of Sydney (School of Information Technologies)
Sydney, Australia, July 2013 - September 2013
Visiting scholar at the School of IT of the University of Sydney.
Programming Languages and Paradigms (COMP3109)
Microsoft Research
Redmond, USA, April 2009 - July 2009
During my internship at MSR i worked with my mentor Nikolai Tillmann
on SPUR, a tracing JIT compiler.
SPUR: A Trace-Based JIT Compiler for CIL
Second International School on Trends in Concurrency (TIC08)
Prague, Czech Republic, June 22-27, 2008
Third International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES07)
L'Aquila, Italy, July 15-20, 2007
Second International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES06)
L'Aquila, Italy, July 23-29, 2006
T-CREST (ICT)
T-CREST is a ICT FP-7 STREP project funded by the European Commission. The
goal is to develop new time-predictable hardware components (processors,
memory/cache interfaces, Network-on-Chip, etc) and the corresponding
software tools.
The LLVM Compiler Infrastructure
Open source compiler infrastructure for static and dynamic compilation. LLVM
is the target of our compiler generator. In addition, the LLVM JIT is used
in our simulator for binary translation.
Technical University of Denmark
I spent two years in Copenhagen/Lyngby.
Ecole Normale Supérieure de Lyon
I spent two years in Lyon at the COMPSYS team.
Vienna University of Technology
My home university in Vienna, Austria.
Christian Doppler Laboratory
Previously, I worked at the Christian Doppler Laboratory - Compilation
Techniques for Embedded Processors.
EPICOpt
The follow-up project to the Christian Doppler Laboratory called EPICOpt
(Optimal Code Generation for Explicitly Parallel Processors).