Version November 2022

In this project, you will:

1. discover a design framework for integrated circuits (Virtuoso Platform)

2. use a physical design kit (PDK) for a CMOS 45nm technology (gpdk045)

3. design (layout) and characterize a digital standard-cell (TSPC Flip-Flop)

Part I: Virtuoso Environment

• Design environment
  • Design project
  • Virtuoso
  • Library Manager
  • Analysis of a standard-cell

Part II: INV cell Characterization

• Introduction
  • Choosen parameters for all simulations
• Tutorial : Fall transition time of an invertor
  • Simulation environment
  • Characterization
• Propagation times
  • Fall propagation time
  • Rise propagation time

Part III: TSPCFF design netlist preparation

• TSPCFF netlist and environment preparation
• Directory setup
• TSPCFF netlist
• Invertor parametrization

Part IV: TSPCFF cell Characterization

• Rise propagation time of the TSPCFF
  • Usefull parameters for a D flip-flop
  • Code update: board.vams
  • Code update: testbench.sv
  • Simulation
• Setup time
  • Setup time behavior exploration
  • Combined extraction of setup and propagation time
  • Bonus: What about hold-time ?

Part V: TSPCFF cell Layout

• Layout
  • TSPCFF layout
  • Parasitic extraction
  • Contents of your report

Part VI: TSPCFF cell Final characterization

• Introduction
  • Extraction of the propagation times
  • Results
  • Extraction of the setup time

Part VII: TSPCFF cell Optimization

• Optimization strategy

Appendices

• Documentation
  • Spectre
  • Verilog-A
• Expected final report