florian   Associate Professor
Florian Brandner
LTCI
Télécom ParisTech
Université Paris-Saclay

About Me


Contact Information

Florian Brandner
Office C216-1
Télécom ParisTech
46, rue Barrault
75013 Paris
France

+33 (0)1 45 81 71 76
florian.brandner (at) telecom-paristech.fr


Personal Information

My curriculum vitae can be downloaded as PDF in english and french.

I am member of the ACM and the HiPEAC network of excellence.


Research Interests

My current research topic is on compiler-backend optimizations for embedded processors, foremost VLIW-style architectures, in the context of real-time systems. In contrast to traditional compilation, the goal here is not to reduce the execution time of the average-case. Instead the worst-case execution time (WCET) is optimized. The main challenge is that during the compilation process it is not yet clear which code paths will actually be relevant for the WCET.

During a two-year stay in France at the COMPSYS Team of the ENS de Lyon, I have been working on traditional compilation, particularly on trying to exploit properties of Static Single Assignment form (SSA) in order to improve the compilation time and code quality of dynamic as well as static compilers.

Previously, I worked on processor description languages, where compiler components, cycle-accurate simulators, and even hardware models (VHDL) were derived from a given processor specification. The compiler generation is focused on the open source compiler infrastructure LLVM. The simulator uses a mixed approach based on interpretation and dynamic compilation via the LLVM JIT compiler. See my PhD thesis and the publications below for more details.

In general I'm interested in code generation techniques, register allocation, instruction scheduling and instruction bundling for VLIW architectures, as well as simulation techniques, such as dynamic binary translation. Recently, I also found interest in problems related to computing under timing constraints (real-time systems, etc.).

Teaching


2016/2017

Systéme d'exploitation et langage C (INF104/SELC)
Lecturer: F. Brandner (Group 1 and 2)
INFO Course Material

Support d'exécution (SE201)
Lecturer: F. Brandner
INFO

Programmation concurrente (SE205)
Lecturer: L. Pautet, F. Brandner
INFO Course Material

Systémes Temps Réel Embarqués Critiques (SE301 or STREC for master SAR/SETI/COMASIC)
Lecturer: T. Robert, L. Pautet, M. Jan, E. Borde, F. Brandner
INFO (SETI/COMASIC)

Architecture Matérielle des Ordinateurs (SJTU-ParisTech, CS443)
Lecturer: F. Brandner
INFO

Projet de programmation (INF280)
Lecturer: A. Amarilli, B. Meyer, F. Brandner
INFO

2015/2016

Systéme d'exploitation et langage C (INF104/SELC)
INFO Supports

Support d'exécution (SE201)
Lecturer: T. Robert, F. Brandner
INFO Supports

Programmation concurrente (SE205)
Lecturer: L. Pautet, F. Brandner
INFO Supports

Master SAR/COMASIC (INF940)
Lecturer: T. Robert, L. Pautet, M. Jan, E. Borde, F. Brandner
INFO

Architecture Matérielle des Ordinateurs (SJTU-ParisTech, AMO402)
Lecturer: F. Brandner
INFO

Parallélisme (ENSTA, IN203)
Professor: F. Brandner, P. Kestener
INFO Supports


2014/2015 (ENSTA)

Parallélisme (IN203)
Professor: F. Brandner, P. Kestener
INFO

Compilation et Optimisations de code (B6-4)
Professor: B. Monsuez, F. Brandner
INFO

Algorithmique et Programmation (en Python) (IN101)
Professor: F. Stulp, F. Brandner, A. Gepperth
INFO

Projet informatique (IN104)
Professor: F. Stulp
INFO


2013/2014 (ENSTA)

Systèmes Electroniques Embarqués (ES430)
Professor: Omar Hammami
Exercises
INFO

Systèmes d'exploitation (IN102)
Professor: Bertrand Collin
INFO

Research


External Sources

Google Scholar MS Academic Search DBLP

Projects

Time-Predictable Cache Management for Real-Time Systems (TP-CoMFORT)
Mathieu Jan, Farouk Hebbache (CEA LIST), Florian Brandner, Laurent Pautet (Télécom ParisTech)
CEA 2016-2019

Automatic Frequency and Voltage Scaling of Programs (AAFUP)
Gérard Memmi (Télécom ParisTech), Pierre Jouvelot, Corinne Ancourt (Mines ParisTech), Florian Brandner
Intercarnot 2016-2017

Profiling Metrics and Techniques for the Optimization of Real-Time Programs (PM-TOP)
Florian Brandner, Mathieu Jan (CEA LIST), Albert Cohen (INRIA/ENS), and Amine Naji (ENSTA ParisTech)
Digiteo 2014-0741D, 2014-2017


Proceedings

Proceedings of the 11th Workshop on Optimizations for DSP and Embedded Systems
Florian Brandner, and Tom Vander Aa (Editors)
Orlando, FL, USA, 2014
ACM ICPS, ACM DL Author-ize serviceLINK

Proceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems
Florian Brandner, and Tom Vander Aa (Editors)
Shenzhen, China, 2013
ACM ICPS, ACM DL Author-ize serviceLINK


Book Chapters

Propagating Information using SSA
Florian Brandner, and Diego Novillo
SSA-based Compiler Design,
Fabrice Rastello and Florent Bouchez (Editors)
Springer, 2016, INFO

DSP Instruction Set Simulation
Florian Brandner, Nigel Horspool, and Andreas Krall
Handbook of Signal Processing Systems (2nd Edition),
S.S. Bhattacharyya, E.F. Deprettere, R. Leupers, and J. Takala (Editors)
Springer, 2013, INFO, FULLTEXT, CHAPTER

DSP Instruction Set Simulation
Florian Brandner, Nigel Horspool, and Andreas Krall
Handbook of Signal Processing Systems,
S.S. Bhattacharyya, E.F. Deprettere, R. Leupers, and J. Takala (Editors)
Springer, 2010, INFO, FULLTEXT, CHAPTER


International refereed Journals

Studying Optimal Spilling in the Light of SSA
Quentin Colombet, Florian Brandner, and Alain Darte
ACM Transactions on Architecture and Code Optimization (TACO), ACM
Volume 11(4): (2015), ACM DL Author-ize servicePDF

Refinement of Worst-Case Execution Time Bounds by Graph Pruning
Florian Brandner and Alexander Jordan
Computer Languages, Systems & Structures (COMLAN), Elsevier
Volume 40(3-4): 155-170 (2014)
online: 28. Sep. 2014, DOI

Criticality: Static Profiling for Real-Time Programs
Florian Brandner, Stefan Hepp, and Alexander Jordan
Real-Time Systems (RTS)
Volume 50(3): 377-410 (2014)
online: 31. Oct. 2013, DOI

Elimination of Parallel Copies using Code Motion on Data Dependence Graphs
Florian Brandner and Quentin Colombet
Computer Languages, Systems & Structures (COMLAN), Elsevier
Volume 39(1): 25-47 (2013)
online: 5. Oct. 2012, DOI

Automatic Generation of Compiler Backends
Florian Brandner, Viktor Pavlu, and Andreas Krall
Software: Practice and Experience (SPE), John Wiley & Sons, Ltd
Volume 43(2): 207-240 (2013)
online: 16. Jan. 2012, DOI


International refereed Conferences

Experimental Energy Profiling of Energy-Critical Embedded Applications
Kameswar Rao Vaddina, Florian Brandner, Gerard Memmi, and Pierre Jouvelot
Symposium on Green Networking and Computing (SGNC) part of SoftCOM 2017
too appear, 2017

Efficient Context Switching for the Stack Cache: Implementation and Analysis (Outstanding Paper Award)
Sahar Abbaspour, Florian Brandner, Amine Naji, and Mathieu Jan
23th International Conference on Real-Time and Network Systems (RTNS)
Lille, France, 2015, ACM DL Author-ize servicePDF

Splitting Functions into Single-Entry Regions
Stefan Hepp and Florian Brandner
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)
New Delhi, India, 2014, ACM DL Author-ize servicePDF

A Loosely Synchronizing Asynchronous Router for TDM-Scheduled NOCs
Ioannis Kotleas, Dean Humphreys, Rasmus Bo Sørensen, Evangelia Kasapaki, Florian Brandner, and Jens Sparsø
International Symposium on Networks-on-Chip (NOCS)
Ferrara, Italy, 2014, DOI

Static Analysis of Worst-Case Stack Cache Behavior
Alexander Jordan, Florian Brandner, and Martin Schoeberl
21th International Conference on Real-Time and Network Systems (RTNS)
Sophia-Antipolis, France, 2013, ACM DL Author-ize servicePDF

Static Profiling of the Worst-Case in Real-Time Programs (Best Paper Award)
Florian Brandner, Stefan Hepp, and Alexander Jordan
20th International Conference on Real-Time and Network Systems (RTNS)
Pont-à-Mousson, France, 2012, ACM DL Author-ize servicePDF

Static Routing in Symmetric Real-Time Network-on-Chips
Florian Brandner and Martin Schoeberl
20th International Conference on Real-Time and Network Systems (RTNS)
Pont-à-Mousson, France, 2012, ACM DL Author-ize servicePDF

A Statically-Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time Systems
Martin Schoeberl, Florian Brandner, Evangelia Kasapaki, and Jens Sparsø
6th International Symposium on Networks-on-Chip (NOCS)
Kongens Lyngby, Denmark, 2012, DOI

Copy Elimination on Data Dependence Graphs
Florian Brandner and Quentin Colombet
27th Symposium On Applied Computing (SAC-PL)
Riva del Garda, Italy, 2012, ACM DL Author-ize servicePDF

A Non-Iterative Data-Flow Algorithm for Computing Liveness Sets in Strict SSA Programs
Benoit Boissinot, Florian Brandner, Alain Darte, Benoît Dupont De Dinechin, and Fabrice Rastello
International Symposium on Programming Languages and Systems (APLAS)
Kenting, Taiwan, 2011, DOI

Studying Optimal Spilling in the Light of SSA
Quentin Colombet, Florian Brandner, and Alain Darte
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)
Taipei, Taiwan, 2011, ACM DL Author-ize servicePDF

Execution Models for Processors and Instructions
Florian Brandner, Viktor Pavlu, and Andreas Krall
28th Norchip Conference
Tampere, Finland, 2010

SPUR: A Trace-Based JIT Compiler for CIL
Michael Bebenita, Florian Brandner, Manuel Fahndrich, Francesco Logozzo, Wolfram Schulte, Nikolai Tillmann, and Herman Venter
International Conference on Object Oriented Programming Systems Languages and Applications (OOPSLA)
Reno, USA, October, 2010, ACM DL Author-ize servicePDF

Completeness of Automatically Generated Instruction Selectors
Florian Brandner
21st International Conference on Application-specific Systems, Architectures and Processors (ASAP)
Rennes, France, July, 2010, DOI

RTTM: Real-Time Transactional Memory
Martin Schoeberl, Florian Brandner, and Jan Vitek
25th Symposium On Applied Computing (SAC-RTS)
Sierre, Switzerland, March, 2010, ACM DL Author-ize servicePDF

Stack Allocation of Objects in the Cacao Virtual Machine
Peter Molnar, Andreas Krall, and Florian Brandner
7th International Conference on the Principles and Practice of Programming in Java (PPPJ)
Calgary, Canada, August, 2009, ACM DL Author-ize servicePDF

Embedded JIT Compilation with CACAO on YARI
Florian Brandner, Martin Schoeberl, and Tommy Thorn
12th IEEE International Symposium on Object/component/service-oriented Real-time distributed Computing (ISORC)
Tokyo, Japan, March, 2009, DOI

Generalized Instruction Selection using SSA-Graphs
Dietmar Ebner, Florian Brandner, Bernhard Scholz, Andreas Krall, Peter Wiedermann, and Albrecht Kadlec
ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)
Tucson, USA, June, 2008, ACM DL Author-ize servicePDF

Compiler Generation from Structural Architecture Descriptions
Florian Brandner, Dietmar Ebner, and Andreas Krall
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)
Salzburg, Austria, October, 2007, ACM DL Author-ize servicePDF

Effective Compiler Generation by Architecture Description
Stefan Farfeleder, Andreas Krall, Edwin Steiner, and Florian Brandner
ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)
Ottawa, Canada, June, 2006, ACM DL Author-ize servicePDF


International refereed Workshops

Worst-Case Execution Time Analysis of Predicated Architectures
Florian Brandner and Amine Naji
Workshop on Worst-Case Execution Time Analysis (WCET)
Dubrovnik, Croatia, 2017, PDF

Eager Stack Cache Memory Transfers
Amine Naji and Florian Brandner
Workshop on Worst-Case Execution Time Analysis (WCET)
Toulouse, France, 2016, PROC, PDF

A Comparative Study of the Precision of Stack Cache Occupancy Analyses
Amine Naji and Florian Brandner
Junior Researcher Workshop on Real-Time Computing (JRWRTC)
Lille, France, 2015, PROC, PDF

Alignment of Memory Transfers of a Time-Predictable Stack Cache
Sahar Abbaspour and Florian Brandner
Junior Researcher Workshop on Real-Time Computing (JRWRTC)
Versailles, France, 2014, PROC, PDF

Lazy Spilling for a Time-Predictable Stack Cache: Implementation and Analysis
Sahar Abbaspour, Alexander Jordan, and Florian Brandner
Workshop on Worst-Case Execution Time Analysis (WCET)
Madrid, Spain, 2014, PDF

A Time-predictable Stack Cache
Sahar Abbaspour, Florian Brandner, and Martin Schoeberl
Workshop on Software Technologies for Embedded and Ubiquitous Systems (SEUS)
Paderborn, Germany, 2013, PDF

Studying Spilling in the Light of SSA
Quentin Colombet, Florian Brandner, and Alain Darte
Workshop on Compilers for Parallel Computing (CPC)
Padova, Italy, 2012

Modeling Application-Specific Processors for the Use in Cyber-Physical Systems
Florian Brandner, Viktor Pavlu, and Andreas Krall
Workshop on Software Language Engineering for Cyber-physical Systems (WS4C)
Berlin, Germany, October, 2011

Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach
Martin Schoeberl, Pascal Schleuniger, Wolfgang Puffitsch, Florian Brandner, Christian W. Probst, Sven Karlsson, and Tommy Thorn
Workshop on Practice, Predictability and Performance in Embedded Systems (PPES)
Grenoble, France, March, 2011, PDF

Automatic Tool Generation from Structural Processor Descriptions
Florian Brandner
15th Biennial Workshop on Programmiersprachen und Grundlagen der Programmierung (KPS)
Maria Taferl, Austria, October, 2009, PDF

Precise Simulation of Interrupts using a Rollback Mechanism
Florian Brandner
12th International Workshop on Software and Compilers for Embedded Systems (SCOPES)
Nice, France, April, 2009, ACM DL Author-ize servicePDF

Completeness of Instruction Selector Specifications with Dynamic Checks
Florian Brandner
8th International Workshop on Compiler Optimization Meets Compiler Verification (COCV)
York, England, 2009

Fast and Accurate Simulation using the LLVM Compiler Framework
Florian Brandner, Andreas Fellnhofer, Andreas Krall, and David Riegler
1st Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO)
Paphos, Cyprus, January, 2009, PDF

Leveraging Predicated Execution for Multimedia Processing
Dietmar Ebner, Florian Brandner, and Andreas Krall
Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia)
Salzburg, Austria, October, 2007

Static Verification of Global Heap References in Java Native Libraries
Andreas Krall, Christian Thalinger, Dietmar Ebner, and Florian Brandner
Workshop on Semantics, Program Analysis, and Computing Environments for Memory Management (SPACE)
Charleston, USA, January, 2006


Technical Reports

Subgraph-Based Refinement of Worst-Case Execution Time Bounds
Florian Brandner and Alexander Jordan
ENSTA Technical Report, 00978015
Palaiseau, France, April, 2014, PDF INFO

Parallel Copy Elimination on Data Dependence Graphs
Florian Brandner and Quentin Colombet
INRIA Technical Report, RR-7535
Lyon, France, September, 2011, PDF INFO

Computing Liveness Sets for SSA-Form Programs
Florian Brandner, Benoit Boissinot, Alain Darte, Benoît Dupont De Dinechin, and Fabrice Rastello
INRIA Technical Report, RR-7503
Lyon, France, January, 2011, PDF INFO

SPUR: A Trace-Based JIT Compiler for CIL
Michael Bebenita, Florian Brandner, Manuel Fahndrich, Francesco Logozzo, Wolfram Schulte, Nikolai Tillmann, and Herman Venter
Technical Report, Microsoft Research, MSR-TR-2010-27
Redmond, USA, March, 2010, PDF

Embedded JIT Compilation with CACAO on YARI
Florian Brandner, Tommy Thorn, and Martin Schoeberl
Technical Report, Institute of Computer Engineering, Vienna University of Technology, RR 35/2008
Vienna, Austria, June, 2008, PDF INFO


Project Reports

D2.1 - Software Simulator of Patmos
Florian Brandner
Report of T-CREST Deliverable D2.1, 2012, PDF

D5.2- Initial Compiler Version
Florian Brandner, Stefan Hepp, and Daniel Prokesch
Report of T-CREST Deliverable D5.2, 2012, PDF


Thesis

Compiler Backend Generation from Structural Processor Models
Florian Brandner
PhD thesis, Vienna University of Technology, 2009, PDF


Talks

The Time-Predictable Processor Patmos and its Tool Chain
Seminar at the SEN team of the COMELEC Department of Télécom ParisTech
April 6, 2017, Paris, France

Time-predictable (stack) caches and their analysis
Meeting of the Working Group "Optimization of Real-Time Systems" (OVSTR)
October 15, 2015, Paris, France

Profiling Metrics and Techniques for the Optimization of Real-Time Programs: Analysis of Method Cache Extensions
DigiCosme Research Days
March 23, 2015, Gif-sur-Yvette, France

Lazy Spilling for a Time-Predictable Stack Cache: Implementation and Analysis
LRI, ParSys
Host: Christine Eisenbeis
October 14, 2014, Gif-sur-Yvette, France

Refinement of Worst-Case Execution Time Bounds by Graph Pruning
8th Meeting of the French Compilation Community
July 2, 2014, Nice, France

Refinement of Worst-Case Execution Time Bounds by Graph Pruning
VERIMAG
Host: Florence Maraninchi
April 3, 2014, Grenoble, France, PDF

Static Scheduling for Time-Predictable Networks-on-Chip
INRIA Rocquencourt (AOSTE)
Host: Dumitru Potop Butucaru
February 7, 2014, Rocquencourt, France, PDF

Static Analysis of Worst-Case Stack Cache Behavior
7th Meeting of the French Compilation Community
December 6, 2013, Dammarie Les Lys, France, PDF

Time-Predictable Communication in Networks-on-Chip
ENS de Lyon
Host: Alain Darte
February 14, 2013, Lyon, France, PDF

Static Scheduling for Time-Predictable Networks-on-Chip
Danmarks Tekniske Universitet, DTU Informatik
Host: Martin Schöberl
February 24, 2012, Copenhagen, Denmark, PDF

'Optimal' Spilling using Integer Linear Programming
Quentin Colombet, Florian Brandner, and Alain Darte
Vienna University of Technology
Host: Jens Knoop
Mai 27, 2011, Vienna, Austria, INFO

Compiler-driven Optimization of the Worst-Case Execution Time
Florian Brandner, and Alain Darte
Workshop Analyse to Compile, Compile to Analyse (ACCA)
April 3, 2011, Chamonix, France

Instruction Selection using PBQP
MEDIACOM Project Meeting
January 18, 2011, Grenoble, France

Completeness of Instruction Selectors
2nd Meeting of the Communauté Française de Compilation
December 9, 2010, Aussois, France, PDF

Automatic Compiler Generation from Structural Processor Models
Danmarks Tekniske Universitet, DTU Informatik
Host: Martin Schöberl
August 4, 2010, Copenhagen, Denmark, PDF

Automatic Compiler Generation from Structural Processor Models
Institut de Recherche en Informatique et Systèmes aléatoires, IRISA
Host: Steven Derrien
October 19, 2010, Rennes, France, PDF


Community Services

Co-Cordinator of the DigiCosme Real-time Systems Working Group (OVSTR)
Co-Cordinator of the French Compilation Group (2013-2017)

Organization Committee:
CC 2018
RTSS 2017
ETR 2017
RTNS 2014

Co-organizer/Co-chair:
Poster Chair of CGO 2016
9th Meeting of the French Compilation Community
ODES 2014
ODES 2013

Program Committee:
DATE 2018 (TPC of topic E2)

RTNS 2017
SEAA 2017
WCET 2017
VECoS 2017
DATE 2017 (TPC of topic E2)

VECoS 2016 RTNS 2016 SEAA 2016 ARCS 2016 CGO 2016
VECoS 2015, RTNS 2015, SEAA 2015, ARCS 2015, PECCS 2014, PECCS 2013

Session Chair:
CASES 2011

External Reviewer:
DATE 2015, LCTES 2012, FPL 2012, WCET 2012, RTNS 2012, LPAR 2012, DATE 2012, CASES 2011, CC 2011, CGO 2011, PACT 2010, LCTES 2009, SCOPES 2008, PPPJ 2008, CASES 2008, PLDI 2006

Journal Reviewer:
Transactions on Architecture and Code Optimization (TACO), 2015 - 2017
ACM Transactions on Design Automation of Electronic Systems (TODAES), 2016 - 2017
Real-Time Systems (TIME), 2014 - 2017
International Journal of Critical Computer-Based Systems (IJCCBS), 2016
Journal of Cryptographic Engineering (JCEN), 2016
Science of Computer Programming (SCICO), 2016
Journal of Systems Architecture (JSA), 2013 - 2016
ACM Transactions in Embedded Computing Systems (TECS), 2012 - 2015
Computing (COMP), 2013
Parallel Computing (PARCO), 2013
Software: Practice and Experience (SPE), 2012
EURASIP Journal on Embedded Systems (JES), 2011 - 2012
IEEE Transactions on Circuits and Systems for Video Technology (TCSVT), 2010

Misc


International Experience

Shanghai Jiao Tong University-ParisTech Elite Institute of Technology (SPEIT)
Shanghai, China, November/December 2015
Lecturer of a course on computer architecture at SPEIT.

University of Sydney (School of Information Technologies)
Sydney, Australia, July 2013 - September 2013
Visiting scholar at the School of IT of the University of Sydney.
Programming Languages and Paradigms (COMP3109)

Microsoft Research
Redmond, USA, April 2009 - July 2009
During my internship at MSR i worked with my mentor Nikolai Tillmann on SPUR, a tracing JIT compiler.
SPUR: A Trace-Based JIT Compiler for CIL


Summer Schools

Second International School on Trends in Concurrency (TIC08)
Prague, Czech Republic, June 22-27, 2008

Third International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES07)
L'Aquila, Italy, July 15-20, 2007

Second International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES06)
L'Aquila, Italy, July 23-29, 2006


Links

T-CREST (ICT)
T-CREST is a ICT FP-7 STREP project funded by the European Commission. The goal is to develop new time-predictable hardware components (processors, memory/cache interfaces, Network-on-Chip, etc) and the corresponding software tools.

The LLVM Compiler Infrastructure
Open source compiler infrastructure for static and dynamic compilation. LLVM is the target of our compiler generator. In addition, the LLVM JIT is used in our simulator for binary translation.

Technical University of Denmark
I spent two years in Copenhagen/Lyngby.

Ecole Normale Supérieure de Lyon
I spent two years in Lyon at the COMPSYS team.

Vienna University of Technology
My home university in Vienna, Austria.

Christian Doppler Laboratory
Previously, I worked at the Christian Doppler Laboratory - Compilation Techniques for Embedded Processors.

EPICOpt
The follow-up project to the Christian Doppler Laboratory called EPICOpt (Optimal Code Generation for Explicitly Parallel Processors).

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